TDP0604: Regarding the operation of the DDC level shifter when there is an internal pull-up/pull-down (which the master device has) on the LV_DDC_SDA/SCL side. and about the solution.

Masita-san

With the TDP0604 internal DDC buffer disabled with MODE pin in the 'R' state (20k to GND), you have to connect the LV side for the snooping function. 

Is the Master DDC an open drain I/O? The TDO0604 has 2 bidirectional, open-drain buffers specifically designed to support up and down-translation between the low voltage (LV) side DDC-bus and the high voltage (HV) 5-V DDC-bus. The LV_DDC_SDA and LV_DDC_SCL are internally pulled up to VIO.

A LOW level on LV side (below VILC = 0.08 × VIO) turns the corresponding HV driver (either SDA or SCL) on and drives HV side down to VHVOL. When LV side rises above approximately 0.10 × VIO, the HV pulldown driver is turned off and the internal pullup resistor pulls the pin HIGH. When HV side falls first and goes below 1.6-V, a CMOS hysteresis input buffer detects the falling edge, turns on the LV driver, and pulls LV down to approximately VLVOL = 0.16 × VIO. The LV side pulldown is not enabled unless the LV voltage goes below VILC. If the LV side low voltage goes below VILC, the HV side pulldown driver is enabled until LV side rises above (VILC + ΔVT-HYST), then HV side, if not externally driven LOW, continues to rise being pulled up by the external pullup resistor.

Thanks

David

Dear David.

Thank you for answering.

Am I correct in saying that the HV side should be left open if the DDC buffer is disabled and external DDC buffer ?

I have created a PCB with LV and HV side traces.

A pattern cut is required if the HV side must be open. so I'm considering about that.

Best regards,

Yuji Mashita.

Masita-san

You have two options of implementing the DDC snooping using TDP0604.

1. Snooping on the LV side. Leave HV side open, disable the TDP0604 internal DDC buffer

2. Snooping on the HV side. Leave LV side open, enable the TDP0604 internal DDC buffer

So your understanding is correct.

Thanks

David

Dear David.

Thank you for answering.

Sorry to bring the topic back, but is it a problem that TDP0604's LV_DDC_SDA/SCL has built-in pull-ups

when the master of DDC is not open drain but push-pull?

If there is a problem, is the solution presented in solution 2 the optimal solution?

Best regards,

Yuji Masita.

Masita-san

Since snooping is only used to differentiate between HDMI1.4 and 2.0 and this is a DP++ to DVI design, I would use the external level shifter and leave both LV and HV side open since you actually do not need the snooping function.

But if snooping is needed, I would agree with you on solution 2.

Thanks

David

Dear David.

Thank you for answering.

I understand that there is a method to leave both LV and HV sides open in addition to Solution 2.

To clarify and prevent myself from making the same mistake again, if the DDC master side is push-pull, will the DDC buffer of TDP0604 not function properly?

The following waveform was observed, but would it be explainable if the DDC master side is push-pull?

When connecting following the Figure 8-5 in the datasheet, with the DDC buffer enabled,LV side waveform:

ch1 is SDA,ch2 is SCL.

At the same time on HVside waveform:

Compare with LV side and HV side SDA NAK-like signal riseup timing:

now ch1 is LV side SDA ,ch2 is HV side SDA.

Close up:

It seems that the LV side SDA is 800ns faster than the HV side SDA.

The waveform when DDC buffer is disabled in the situation where following the Figure 8-5 in the datasheet for the connection,

LV side waveform:

Best regards,

Yuji Masita

Masita-san

The TDP1204 has integrated pullups to VIO on the DDC LV pins. Therefore, no external pull-ups shall be present between the TDP1204's DDC LV pins and DDC host when using TDP1204's DDC buffer.

If you look at the waveform, when HV side falls first and goes below 1.6-V, a CMOS hysteresis input buffer detects the falling edge, turns on the LV driver, and pulls LV down to approximately VLVOL = 0.16 × VIO. With VIO being 3.3V, the VLVOL will be 0.528V. But with the internal 100k pullup on SDA, the scope waveform shows the SDA being pulled up to 1.7V.

So I believe you need to use an external DDC buffer and following the connection as shown in Figure 8-6 of the TDP1204 datasheet.

Thanks
David

Dear David.

May I ask you one last question?

Looking at the TDP0604 datasheet and reference circuit, a circuit is shown that allows

an external DDC buffer to be used.

Does this mean that the TDP0604 DDC buffer is often not available, as in this case?

Could you please tell me the conditions on the master side

when an external DDC buffer is not used (i.e., when Figure 8-5 of the datasheet is applicable)?

Are there any conditions other than being open-drain and having no pull-up resistors?

Best regards,

Yuji Masita.