• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 33 subscribers
  • Views 483 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TUSB8041: VDD and VDD33 sequence when not using external reset IC

Hisao Uchikoshi
Genius 14980 points
Part Number: TUSB8041


Hi Experts,

My customer does not want to use external reset IC. Please confirm either of below is correct.

  1. Apply VDD(1.1V) at first then after elapsing 10us, VDD33 can be applied. GRSTz can be left open.
  2. Apply VDD(1.1V) at first then after elapsing 10us, VDD33 can be applied. Connected a capacitor to GRSTz pin to satisfy 3ms after VDD33 becomes stable..

I believe #1 is enough but please confirm it.

Regards,

Uchikoshi

  • +1
    TI__Intellectual 2850 points

    Hi Uchikoshi,

    GRSTz cannot be floating or open, so only option 2 works.

    Thank you,

    SLW

  • 0 in reply to Stanton Weaver
    TI__Genius 14980 points

    Hi SLW,

    Thank you for your reply. I am confusing below note of table 7.6 on page 11 

    > There is no power-on relationship between VDD33 and VDD unless GRSTz is only connected to a capacitor to GND. Then VDD must be stable minimum of 10 μs before the VDD33.

    I understand this sentence meaning is as following.

    If VDD(1.1V) is applied at first then VDD33 is applied after 10us at least, it is OK to add any value of capacitor on GRSTz pin. Is this understanding correct? 

    Also, on EVM, it looks that 3.3V is applied at first then 1.1V is applied. GRSTz pin is connected with only1uF which seems not to satisfy 3ms. Is there something wrong? Should use reset IC on evm schematics?

    Regards,

    Uchikoshi

  • +1 in reply to Hisao Uchikoshi
    TI__Genius 14980 points

    Hi SLW,

    Thank you for your reply. I am confusing below note of table 7.6 on page 11 

    > There is no power-on relationship between VDD33 and VDD unless GRSTz is only connected to a capacitor to GND. Then VDD must be stable minimum of 10 μs before the VDD33.

    I understand this sentence meaning is as following.

    If VDD(1.1V) is applied at first then VDD33 is applied after 10us at least, it is OK to add any value of capacitor on GRSTz pin. Is this understanding correct? 

    Also, on EVM, it looks that 3.3V is applied at first then 1.1V is applied. GRSTz pin is connected with only1uF which seems not to satisfy 3ms. Is there something wrong? Should use reset IC on evm schematics?

    Regards,

    Uchikoshi

  • 0 in reply to Hisao Uchikoshi
    TI__Intellectual 2850 points

    Uchikoshi,

    It is better to ramp 1.1v and 3.3v at the same time and add 0.1uf cap on GRSTz pin. We will validate this issue on the bench. 

    Thanks,

    Stanton