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DS90UB940N-Q1: Output mipi clock is strange

Part Number: DS90UB940N-Q1

Hi, 

We are going to connect DS90UB947 or DS90UB949A to DS90UB940N.

However, MIPI CLOCK is output differently than expected.

When we put 1280x720@30 (PCLK=37.2MHz) video into DS90UB940N and set YUV422, we expected output MIPI_CLK to be around 148.8MHz.

(By the formula MIPI_CLK*MIPI_LANE=PCLK*BPP)

However, the actual MIPI_CLK is measured at about 130 MHz.  It is output as if BPP is 14 bits.

Also, if the video format is converted to RGB888 and the BPP is converted to 24bit, it seems that the output MIPI_CLK should be changed, but it remains unchanged and is about 130MHz.

I tried using the DS90UH947's internal pattern generator just in case, but the result was the same.

When tested with YUV422, the default resolution of the internal pattern generator, 840x485@61.4Hz, MIPI_CLK was expected to be around 100MHz, but the actual output was around 89MHz.

(Similarly, it is output as if it were 14bit BPP.)

I wondered if the MIPI output was strange, so I connected it to an AP and output it with gstreamer. 
However, the video was normally recognized and processed, and the image format (YUV422, RGB888) was recognized normally.

When MIPI-CSI is connected to an IC that converts to Parallel, the output PCLK is the same as the value calculated from the MIPI_CLK output.

(Value calculated as if it were 14bit BPP)

I'm curious as to why this is happening.

Thank You!!!

Regards,

Sujin

  • Sujin,

    Architecturally, when the 940N is used with 4x CSI-2 outputs the MIPI lane rate is always PCLK*7 regardless of the data format. This is mentioned in section 7.4.1 of the datasheet. 

    So for your first example, PCLK = 37.2MHz, which means MIPI output is 37.2*7 = 206.4Mbps/lane = 130.2MHz CSI-2 clock. 

    If you are converting to a lower bit depth for example from RGB888 to YUV422, the result is that you will get 16bpp instead of 24bpp coming out, but the transmission frequency is the same, so the remaining time will just end up as horizontal blanking (idle time) on the bus in LP11. That is allowed by the CSI-2 standard since MIPI CSI-2 does not require discrete horizontal timing to be conveyed. 

    In your second example, the PCLK is ~25.4MHz, so 25.4*7 = 178Mbps/lane = 89MHz CSI-2 clock 

    Best Regards,

    Casey