LMH0303: what happens if the ENABLE is pulled up on 1.45V?

Nan Zhang

Part Number: LMH0303
Other Parts Discussed in Thread: LMH1219

Hi team,

Our customer use the FPGA to pull up or down the ENABLE pin. When the FPGA start to power up ,I/O will output some levels uncontrollably. They test the wave shown below:

LMH0303_0406.pptx

In there test, the wave in yellow is the LHM0303_VCC and the wave in green is LHM0303_ENABLE. We can see that the ENABLE in green is pulled up at 1.45V for several seconds and last 380ms. And then the ENABLE is pulled up to 3.3V.

Would there be any potential risk for the device in such power on sequence？

YOURS

NAN

over 2 years ago

0 Drew Miller1 over 2 years ago

TI__Mastermind 37293 points

Hi Nan,

I would expect this to work fine. The customer would not be able to predict ENABLE behavior while it is 1.45V, but it would work as expected once it is 3.3V.

Thanks,

Drew

0 Nan Zhang over 2 years ago in reply to Drew Miller1

TI__Intellectual 1895 points

Hi Drew,

Thanks for your reply.

I find that the ENABLE is LVCOMS at 3.3V, so the maximum of high level is 2V . So the 1.45V from FPGA would not enable the LMH0303. Am I right?

YOURS

NAN

0 Nan Zhang over 2 years ago in reply to Drew Miller1

TI__Intellectual 1895 points

Hi Drew,

Thanks for your reply.

I find that the ENABLE is LVCOMS at 3.3V, so the maximum of high level is 2V . So the 1.45V from FPGA would not enable the LMH0303. Am I right?

YOURS

NAN

0 Nan Zhang over 2 years ago in reply to Drew Miller1

TI__Intellectual 1895 points

Hi Drew,

Thanks for your reply.

I find that the ENABLE is LVCOMS at 3.3V, so the maximum of high level is 2V . So the 1.45V from FPGA would not enable the LMH0303. Am I right?

YOURS

NAN

0 Drew Miller1 over 2 years ago in reply to Nan Zhang

TI__Mastermind 37293 points

Hi NAN,

Typically I have seen LVCMOS thresholds at 0.3x and 0.7x VDD. Please see excerpt from LMH1219 datasheet below. With that said, V_IH min should be interpreted as the minimum voltage that will guarantee a logic "high". However, it is possible that different devices will have different thresholds, and some devices may interpret logic "high" at a voltage < 0.7 * 3.3V. 1.45V is well outside of the VIL and VIH behavior, so it is hard to predict the behavior. Is there any concern about the device being enabled during this FPGA startup?

Thanks,
Drew

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LMH0303: what happens if the ENABLE is pulled up on 1.45V?