DS90UB941AS-Q1: Set External Reference Clock and dual link mode

Hi Hanyang, Alan

hanyang zhang said:

Modifications:
1. Use External Reference Clock
941 Register 0x56: 0x01 01: External Reference Clock Mode

2.set dual link mode
941 Register 0X5B: 0X03
941 0X5B[2:0] 011 : Forced Dual FPD-Link III Transmitter mode

948 Register0X34: 0X09
948 0X34[4:3] 01: Forced Mode: Dual link

After setting these registers: both 941 and 948 are in dual link mode?

This is correct.

hanyang zhang said:

941 Register status is DUAL_STS_DUAL_STS_P1 0x5A: 0xC9
948 Register status is GENERAL_STATUS 0x1C: 0x33

Correct, 0x33 confirms dual mode.

hanyang zhang said:

1. When REFCLK is set to 105MHZ, the screen can be displayed. Why is there no display on the screen when it is set to 138MHZ. The registers are shown in the picture.

Can you elaborate on on the expected PCLK and video timing of the actual panel? What is changing between the two PCLK setpoints? Refresh rate only? Video Htotal and Vtotal? etc?

Is DSI data input of PatGen being tested?

Is the SoC output data being properly adjusted from 105MHz to 138MHz. Has DSI data from SoC been already verified? What DSI settings are used?

hanyang zhang said:

3. How to set REFCLK and link mode, TI948 can output 1080P 60HZ (PCLK 138MHZ)?
1-lane FPD-Link III input, single-link OpenLDI output
1-lane FPD-Link III Input, Dual Link OpenLDI output
2-lane FPD-Link III Input, dual-link OpenLDI output
2-lane FPD-Link III Input, single-link OpenLDI output
2-lane FPD-Link III Input, single-link OpenLDI output (replicate)

These are all set via the ModeStrap0 value. Let's focus on what is actually being targeted by panel. 2-lane FPD-Link is required due to the PCLK needed. What OLDI configuration is needed?

Regards, 

Logan