Hi,
I am using TBSU in FPGA board.
Now try to test my RTL in FPGA with TBSU phy chip
( FPGA send out clock to TBSU at this moment )
Can I see write/read timing diagram ?
it doesn't match ULPI timing in singaltpa at FPGA side.
I think this maybe related Read but DIR get pulse so early and so long.
1) I need wave form for read/write
2 )I need simulation model for this
