DS90UB947-Q1: EMI reduction

Ryan Wang

Part Number: DS90UB947-Q1

Dear expert,

DS90UB947-Q1 doesn't support SSC (spread spectrum clocking). However, UB947 datasheet shows OpenLDI INPUTS Input Total Jitter Tolerance is 0.2UI max.

Customer use 40M OLDI clock. 0.2UI = 0.2* 12.5ns=2.5ns

Now customer SoC can send 40MHz with 0.25% spread. This is 25ns*0.25% variation which looks within our jitter requirement.

But Now UB947+UB948 always unlock with this 0.25% spread.

Is it normal?

over 2 years ago

0 Hamzeh Jaradat over 2 years ago

TI__Guru** 108010 points

Hello Ryan,

We do not recommend using SSC on the input side of this device unless absolutely necessary for a specific EMC concern. In general this device has been used in many production systems WW which are able to pass common EMC tests at the system level without using SSC on the input. Using SSC on the input will significantly reduce the signal margin on the oLDI side and may need some tuning of fdev/fmod to ensure robust operation vs your PCLK rate and the source output jitter profile.

If it is really very necessary and you must use SSC, then I recommend you use ~0.1-0.15% Fdev, 8.7kHz Fmod. Please try this and let us know.

0 Ryan Wang over 2 years ago in reply to Hamzeh Jaradat

TI__Expert 7435 points

Hamzeh,

Great thanks for your explanation.

We will try accordingly.

0 Ryan Wang over 2 years ago in reply to Hamzeh Jaradat

TI__Expert 7435 points

Hamzeh,

Customer SoC can only send 30kHz Fmod and UB947+UB948 got frequent unlock.

Is there any other way for them?

Thanks

0 Hamzeh Jaradat over 2 years ago in reply to Ryan Wang

TI__Guru** 108010 points

Hello Ryan,

unfortunately, we have not tested other frequency than the mentioned.

Due to the fact that even with 0.1-0.15% they are still getting unlocked, that indicates they have originally high jitter on the input signal, or their link margin is very low due to not optimal hardware design/ cable or connector.

0 Ryan Wang over 2 years ago in reply to Hamzeh Jaradat

TI__Expert 7435 points

Hamzeh,

Thanks

0 Ryan Wang over 2 years ago in reply to Ryan Wang

TI__Expert 7435 points

Hamzeh,

Customer still cannot solve this EMC problem.

Their PCLK is 42.85MHz. EMC spike appear for around every 330KHz.

42.85M/330K=129.85

For below description in UB947 datasheet, below signals appear for every 130 PCLKs. Do you think this is related?

Is there any way to workaround this issue in UB947 registers?

Thanks

0 Hamzeh Jaradat over 2 years ago in reply to Ryan Wang

TI__Guru** 108010 points

Hello Ryan,

I do not believe there is any relation between these.

If you can send me their schematic and/or layout, then I can review that and see if there is any potential root cause.

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DS90UB947-Q1: EMI reduction