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DS125DF111: need to bypass re-timer

MohammadReza Nakhkash
Prodigy 10 points
Part Number: DS125DF111

Hi,

We are experincing various BER issue were we are using the re-timer for an SFP link. The SFP module is connected to a re-timer and from the re-timer is connected to an FPGA.

Since the features of the re-timer like CDR locking and jittering, CTLE and DFE adaptation is also done on the FPGA, we are exploring the option to simply bypass the re-timer so that the data from the SFPs will reach the FPGA intact.

To apply a bypass config to the re-timer, it seems that some of the DFE weights and gains for the CTLE has to be set Manually. Hence we need support to figure out the bypass config.

Best,

Mohammadreza Nakhkash

  • 0
    TI__Mastermind 20512 points

    Hi Mohammadreza,

    How much insertion loss are you expecting in your system, and are you able to observe the HEO/VEO? It's possible the BER issue is due to over equalization if the retimer is placed too close to the signal source.

    Please try the bypass config listed in the programming guide (3.26 Raw mode):
    https://www.ti.com/lit/an/snla323/snla323.pdf

    If this does not improve BER, please also try enabling DFE override 0x15[7] = 1, and verify the DFE tap settings are set to their default values { 0x11[3:0], 0x12[7], 0x12[4:0], 0x20[7:0], 0x21[7:0] }. 

    Thank you,

    Evan