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DS90UB936-Q1: I2C mechanism

Roy Chou1
Genius 16325 points
Part Number: DS90UB936-Q1


Hi Team,

We found that the 936 I2C port has some countermeasure when there is a start bit, but no following action. 

Please see below image. You can see there is I2C start bit in the middle of upper window. And then we continuously sent the I2C command and 936 can receive it.(Ack) 

But we found some chips may miss the command. May you share the mechanism about why our 936 can also receive the I2C command even though there is start bit before it?(Maybe we have I2C timeout?) Thank you.

Regards,

Roy

  • 0
    TI__Genius 16230 points

    Hi Roy,

    Let me look into this. Allow 2 business days.

    Glenn 

  • 0 in reply to Glenn Uranga
    TI__Guru 66880 points

    Hi Roy, 

    Is the I2C master on this local 936 bus?

    Most FPD-Link SerDes devices have I2C timeout mechanisms to prevent it from getting locked up. Maybe those cases where the transaction is missed, it was within the timeout period. You might need to do more investigation on failed/non-failed cases to see if there consistency in delay between start bit and transaction. 

    Either way, this seems like a problem on the bus and not necessarily a problem in our device. I'd advise the customer to actually root-cause fix the spurious start bit.

    Regards, 

    Logan