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SN65DSI84-Q1: sn65dis84 test pattern

Jeff Wang100039
Intellectual 2810 points
Part Number: SN65DSI84-Q1


Hi ,

Could you help generate a dsi84 test pattern register setting?

LVDS:

1920 x 1080

dual lvds

24bpp

dsi blank:

hfp  64      vfp  70

hbp 32      vbp 8

hpw 32      vpw 8

Single lvds clk 71.6M

de polarity: positive，hs vs polarity: negative  

lvds channel : Format2

clock reference: csi

best regards,

jeff wang
  • 0
    TI__Guru**** 179261 points

    Jeff

    You can use the attached DSI Tuner to generate the DSI84 register programming value.

    0647.DSI Tuner 2.1.zip

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    TI__Intellectual 2810 points

    my computer no allow install Java environment, so cannot install dsi tuner 2.1

  • 0 in reply to Jeff Wang100039
    TI__Guru**** 179261 points

    Hi, 

    You can download the Java environment from this link, http://javadl.oracle.com/webapps/download/AutoDL?BundleId=44457. 

    I generated the DSI84 programming value assume RGB888 and DSI CLK frequency of 429.6MHz with divider of 6. I would recommend using the reference clock instead the DSI clock since the reference clock tends to have cleaner jitter than the DSI clock. 

    Fullscreen DSI84_Programming_Value.txt Download 
    //=====================================================================
// Filename   : DSI84_Programming_Value.txt
//
//   (C) Copyright 2013 by Texas Instruments Incorporated.
//   All rights reserved.
//
//=====================================================================
0x09              0x00
0x0A              0x05
0x0B              0x28
0x0D              0x00
0x10              0x26
0x11              0x00
0x12              0x55
0x13              0x00
0x18              0x6c
0x19              0x00
0x1A              0x03
0x1B              0x00
0x20              0x80
0x21              0x07
0x22              0x00
0x23              0x00
0x24              0x00
0x25              0x00
0x26              0x00
0x27              0x00
0x28              0x21
0x29              0x00
0x2A              0x00
0x2B              0x00
0x2C              0x20
0x2D              0x00
0x2E              0x00
0x2F              0x00
0x30              0x08
0x31              0x00
0x32              0x00
0x33              0x00
0x34              0x20
0x35              0x00
0x36              0x00
0x37              0x00
0x38              0x00
0x39              0x00
0x3A              0x00
0x3B              0x00
0x3C              0x00
0x3D              0x00
0x3E              0x00


The PLL_EN bit and SOFT_RESET bit are not set as they need to be set per the recommended sequence defined in the datasheet

    Thanks

    David