Hi team,
customer met a problem as below
sequence as below
pull 1V and 1.8V low then pull up 1.8V, pull up out_enable, pull up 1.1V, pull up resetn. phy_mode is 1, refclksel is 3 setting 40MHz on XI. But then receiver has no response.
questions
1. is there REG that can read if there is CLK output?
2. the CLK should be 60Mhz, right? Is there problem for the configuration during power up?
BRs
Given
