DP83867IS: 4-wire SGMII mode, TX aligned, RX unaligned, TBI through a SERDES on a microsemi board

Hi David,

I am not sure if I understand your question correctly. You are having a SGMII communication issue between DP83867 PHY and ILA?

If so, may I couple question for further debug:

• Are you using trace or cable for SGMII communication?
• Is the length matching between RX and TX?
• If you are using a cable, how long is the cable you are using?

--

Regards,

Hillman Lin

We resolved one of three issues.    RX had a pullup in play, this has been resolved.  The PHY and my serdes are sending idle messages now, but one of the failures is preventing us from moving forward.

The most critical issue now is that:

Something is clobbering my management interface mid configuration.

Code snippet:

//READ OUI1
phy_reg = MSS_MAC_read_phy_reg(g_phy_addr,MII_PHYSID1 );

printf("oui1_reg value: 0x%08X\n\r",phy_reg);

//READ OUI2
phy_reg = MSS_MAC_read_phy_reg(g_phy_addr,MII_PHYSID2 );

printf("oui2_reg value: 0x%08X\n\r",phy_reg);

//READ configuration register 4 (aneg)
phy_reg = MSS_MAC_read_phy_reg(g_phy_addr,MII_CFG4 );

printf("config4 reg value: 0x%08X\n\r",phy_reg);

//READ PHY STRAP CONFIGURATION REG 1
phy_reg = MSS_MAC_read_phy_reg(g_phy_addr,MII_STRAP_STS1 );

printf("strap status 1 reg value: 0x%08X\n\r",phy_reg);

//READ PHY STRAP CONFIGURATION REG 2
phy_reg = MSS_MAC_read_phy_reg(g_phy_addr,MII_STRAP_STS2 );

printf("strap status 2 reg value: 0x%08X\n\r",phy_reg);

printf("MII MANAGEMENT IF: 0x%04X 0x%04X 0x%04X 0x%04X 0x%04X 0x%04X \n\r",MAC->MII_CONFIG
,MAC->MII_COMMAND,MAC->MII_ADDRESS,MAC->MII_CTRL,MAC->MII_STATUS,MAC->MII_INDICATORS);

//WRITE BMCR to enable autoneg
phy_reg = 0x1140;
MSS_MAC_write_phy_reg(g_phy_addr, MII_BMCR, phy_reg);

//READ OUI1
phy_reg = MSS_MAC_read_phy_reg(g_phy_addr,MII_PHYSID1 );
printf("1 oui1_reg value: 0x%08X\n\r",phy_reg);
printf("MII MANAGEMENT IF: 0x%04X 0x%04X 0x%04X 0x%04X 0x%04X 0x%04X \n\r",MAC->MII_CONFIG
,MAC->MII_COMMAND,MAC->MII_ADDRESS,MAC->MII_CTRL,MAC->MII_STATUS,MAC->MII_INDICATORS);
phy_reg = 0x0000;
while(phy_reg != 0x1140)
{
delay(50000);
phy_reg = MSS_MAC_read_phy_reg(g_phy_addr,MII_BMCR);
}
//Update autonegotiation settings
phy_reg = MSS_MAC_read_phy_reg(g_phy_addr,MII_CFG2);
phy_reg &= 0x29C7;
MSS_MAC_write_phy_reg(g_phy_addr, MII_CFG2, phy_reg);

//READ OUI1
phy_reg = MSS_MAC_read_phy_reg(g_phy_addr,MII_PHYSID1 );
printf("2 oui1_reg value: 0x%08X\n\r",phy_reg);
printf("MII MANAGEMENT IF: 0x%04X 0x%04X 0x%04X 0x%04X 0x%04X 0x%04X \n\r",MAC->MII_CONFIG
,MAC->MII_COMMAND,MAC->MII_ADDRESS,MAC->MII_CTRL,MAC->MII_STATUS,MAC->MII_INDICATORS);

//disable RGMII
// phy_reg = 0x0000;
// MSS_MAC_write_phy_reg(g_phy_addr, MII_RGMIICTL, phy_reg);
//enable SGMII
phy_reg = 0x0800;
MSS_MAC_write_phy_reg(g_phy_addr, MII_PHYCR, phy_reg);

//READ OUI1
phy_reg = MSS_MAC_read_phy_reg(g_phy_addr,MII_PHYSID1 );
printf("3 oui1_reg value: 0x%08X\n\r",phy_reg);
printf("MII MANAGEMENT IF: 0x%04X 0x%04X 0x%04X 0x%04X 0x%04X 0x%04X \n\r",MAC->MII_CONFIG
,MAC->MII_COMMAND,MAC->MII_ADDRESS,MAC->MII_CTRL,MAC->MII_STATUS,MAC->MII_INDICATORS);

//WRITE config 4 register bit 7 low
phy_reg = 0x1170;
MSS_MAC_write_phy_reg(g_phy_addr, MII_CFG4, phy_reg);

//READ OUI1
phy_reg = MSS_MAC_read_phy_reg(g_phy_addr,MII_PHYSID1 );
printf("4 oui1_reg value: 0x%08X\n\r",phy_reg);
printf("MII MANAGEMENT IF: 0x%04X 0x%04X 0x%04X 0x%04X 0x%04X 0x%04X \n\r",MAC->MII_CONFIG
,MAC->MII_COMMAND,MAC->MII_ADDRESS,MAC->MII_CTRL,MAC->MII_STATUS,MAC->MII_INDICATORS);

/****
// Reset the PHY.
phy_reg = MSS_MAC_read_phy_reg(g_phy_addr, MII_BMCR);
printf("Prep for reset, BMCR: 0x%04X\n\r",phy_reg);
phy_reg |= BMCR_RESET;
MSS_MAC_write_phy_reg(g_phy_addr, MII_BMCR, phy_reg);
// Power up the PHY.
phy_reg = MSS_MAC_read_phy_reg(g_phy_addr, MII_BMCR);
printf("Soft reset, BMCR: 0x%04X\n\r",phy_reg);
phy_reg &= ~BMCR_PDOWN;
MSS_MAC_write_phy_reg(g_phy_addr, MII_BMCR, phy_reg);
phy_reg = MSS_MAC_read_phy_reg(g_phy_addr, MII_BMCR);
printf("phy should be up, BMCR: 0x%04X\n\r",phy_reg);
****/
//READ configuration register 4 (aneg)
phy_reg = MSS_MAC_read_phy_reg(g_phy_addr,MII_CFG4 );

printf("config4 reg value: 0x%08X\n\r",phy_reg);
}

&&&&&&&&&&&&&&&& Console session &&&&&&&&&&&&&&&&

*****************g_phy_addr=phy_addr=0X0******************
Starting Phy initialization routine
oui1_reg value: 0x00002000
oui2_reg value: 0x0000A231
config4 reg value: 0x000010B1
strap status 1 reg value: 0x00008880
strap status 2 reg value: 0x00000100
MII MANAGEMENT IF: 0x0007 0x0000 0x000E 0x401F 0x0100 0x0000

    <---------------------------------------------------------------------Failure here after writing enable ANEG

I loop on the read to check, and the management interface is held high after the correct read instruction goes out on MDO.

1 oui1_reg value: 0x0000FFFF
MII MANAGEMENT IF: 0x0007 0x0000 0x0002 0x1140 0xFFFF 0x0000  

Hi David,

Could you let me know if my understanding is correct: You are having a SGMII communication issue between DP83867 PHY and ILA?

If so, may I couple question for further debug:

• Are you using trace or cable for SGMII communication?
• Is the length matching between RX and TX?
• If you are using a cable, how long is the cable you are using?

--

Thank you,

Hillman Lin

• Are you using trace or cable for SGMII communication? -trace
  • Is the length matching between RX and TX?       -equal trace length between serializer and the phy (mac layer side) - the spin is to .001 accuracy
• If you are using a cable, how long is the cable you are using? - cable from phy to switch is 2 feet pigtailed to high density connector

Update: 

I decoded 10b to 8b at two times: start of configuration at the assertion of lock to the RX data (4-wire sgmii).  The second is arbitrary, some time after configuration.

First case:

For some time after we wait for phy reconfigured to start sending the desired configuration data.

Second case:

We see k28.5 / D16.2's repeating (it appears that tx and rx are both at idle)

After changing the LED to more desirable sources,

led 0:1011, link established, blink for tx rx act... solid light, indicating no activity with a link established

led 1:0101, 1000BT link established... de-energized, no 1000BT link established

led 2:1101, RX/TX error... constant strobe at default strobe rate, indicates failure of tx OR rx periodically

My link partner is passing through a 10/100/1000 NETGEAR GS308P.

The host is a windows 10 machine.  the only connections on the switch are the host and the phy.

The port with the phy in-socket is flashing- appears to be activity.

It looks like a 10/100 connection is established.

I have used the troubleshooting guide and the datasheet. 

Could you provide and example of the timing and behavior of init -> config -> autonegotiation?

When/how does the phy determine, ANEG with the link rate of 1000Base-T?  Does it happen at the very beginning of a write to restart autonegotiation, or at the first link pulse ?  It's just curious that with or w/o advertising 10/100 I link up under 1GB

Hi David,

Are you able to provide an eye diagram for DP83867 SGMII communication? The picture below is the eye diagram mask requirement for SGMII communication:

If possible, could you try the force mode of SGMII to see rather there is an link down issue. Force mode can be program by register 0x0014 bit [7] to disable auto negotiation and bit [11:10] for speed selection. Please make sure to configure force mode on MAC side for SGMII.

--

Regards,

Hillman Lin

Hi David,

Are you able to provide an eye diagram for DP83867 SGMII communication? The picture below is the eye diagram mask requirement for SGMII communication:

If possible, could you try the force mode of SGMII to see rather there is an link down issue. Force mode can be program by register 0x0014 bit [7] to disable auto negotiation and bit [11:10] for speed selection. Please make sure to configure force mode on MAC side for SGMII.

--

Regards,

Hillman Lin

I am attempting both of these now - my scope may not be sufficient - I'll have to rent one most likely.

Hi David,

Sure, take your time. Let me know if you have more question.

--

Regards,

Hillman Lin

I have to rent a scope, all I have is 1GHz available.

Does the phy produce anything internally to accommodate the eye?  If not will a flood ping from the host be enough?

After forcing sgmii aneg off, I see no change.

Hi David,

Before going into tuning the eye diagram, Are you able to meet the specification of the eye diagram that I share earlier?

For the forcing SGMII Aneg off, did you do the same thing on the MAC side?

--

Thank you,

Hillman Lin

Yes it failed with both mac/phy aneg turned off.

One case seems to work:

Configure mac / phy with the cable unplugged, while polling the register for autonegotiate complete,  PLUG the cable in and it negotiates a link.

Would the auto MDIX flp fail to sync with a link partner that has auto MDIX enabled?  I tested this at an unmanaged switch and a linux machine nic, same result.

The autonegotiation issue looks to be resolved - forcing sgmii it was able to link.  There was a mechnical connection on Bpair where the magnetics meet the cable.

Back to the first issue I had:

I am decoding 10B/8B to 8B and decoding,  at one point SGMII configuration register reads B5 BC 01 40,   this would indicate ANEG ack with a 10Mb external link correct?

Does the phy ever register 10Mb in the config reg when I have disabled 10/100 advertisement?

Full sequence: 

BC B5 01 D8, BC 42 01 D8;   so set 1 and set 2 are correct (at some point after negotiation completes)

I then go into idle.

BC 50 BC 50 BC 50 ...

I have LED's mapped by writing 0x6D5B to register 0x0018.

so

LED 0 = Link established, blink for transmit or receive activity

LED 1 = 1000 BT link established

LED 2 = Receive Error or Transmit Error

The sequence:

Power applied -> end of boot loader -> configure phy -> autonegotiation completes -> register dump -> hold indefinitely

After autonegotiation step completes - 

LED 0 is solid on

LED 1 is OFF

LED 2 is OFF

My host machine shows, "NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None"

During this time, BC 50 BC 50 is constant, yet I would expect LED 1 to be energized, would you agree?

What does it mean if it is not energized?

Update: 

I de-energized the board and ran a voltage through LED 1, the LED has failed - I sampled at the phy pin and it is trying to pull up.  So please disregard the LED1 question.

Next issue.  I attempt to flood ping the phy and LED 2 flashes on every ping, indicating an rx failure.

What is an RX failure defined as in this phy?

Can it be - failure to send the packet, loss of alignment, loss of synchronization, no acknowledge, etc.?

Hi David,

Just want to clarify. Right now, we are able to communicate on SGMII, but there is an issue on the copper side (RJ45) of communication. am I correct on this statement?

• It seems like you are not able to communicate in 1000BaseT, from the register 0x000A and 0x0011 it seems like your link partner PHY is not advertising 1000BaseT. Could you re-read this two register after link up to see any value updated?
• it might be a polarity issue for LED 1 that is not turning on. Could you share the schematic of LED 1 to see rather it is active high or low?
• Regarding to the RX_Error might be cause by the unstable link that we are facing so far.

--

Regards,

Hillman Lin