DP83869HM: EMI / EMC Guidelines for Clock and Other Signals

Hi Harikrishnan,

CLK_OUT can be connected directed to the test point. You may refer to the DP83869 EVM user guide for a reference schematic. 

Which EMI/EMC standards are you trying to follow?

Best regards,

Melissa

Hi Melissa,

The Module has to comply for DO-160G Section 18, Section 19, Section 20 and Section 21.

I just want guidelines to be followed during Layout and PCB Routing to avoid issues during compliance testing. General Guidelines to be followed.

Regards,

Harikrishnan T

Hi Melissa,

Thanks for your reply. I have some more queries

Clocking Architecture:

In my design I have 14 Ethernet Interfaces. 10 was configured as 1000BASE-T and 4 was 100BASE-TX.

For that I am sharing common clock with buffers.

Using MEMS Oscillator SiT8924BA in my design as source and LMK1C1104 as Buffer to share the clock to multiple Ethernet PHYs.

Still my architecture on clock was open, I have two ideas in my mind.

1. Individual Oscillators for Individual PHYs

2. Single Oscillator with multiple clock buffers

Which is the best idea as per your thoughts ? If you have any other ideas please let me know.

For both ideas what is the layout and routing recommendations on clock signals.

Please resolve my queries at the earliest.

Regards,

Harikrishnan T

Hi Melissa,

I need one more clarification, As per datasheet MDC Frequency was 2.5MHz (Typical) to 25MHz (Max).

In IEEE 802.3 Section 22.2.2.13, it was mentioned that the minimum clock period for MDC shall be 400ns (i.e) 2.5MHz.

Is this an error in datasheet, please clarify this query at the earliest.

Regards,

Harikrishnan T

Hi Harikrishnan,

Let me check with my team and get back to you.

Best regards,

Melissa

Hi Harikrishnan,

What MDC frequency are you trying to use? Are you seeing any issues?

Best regards,

Melissa

Hi Melissa,

Actually I am in design phase not in testing phase.

I just need clarity on information in datasheet. That's it.

Regards,

Harikrishnan T

Hi Melissa,

I have one more doubt.

Can we place transformers on opposite sides of PCB (Same Location - Top and Bottom Layer) ?

If we can place that any precautions needs to be taken ?

While I search for layout guidelines for Ethernet Interface, I found this application note from Pulse Electronics.

https://www.pulseelectronics.com/wp-content/uploads/2020/12/Pulse_Layout-Considerations-v7.pdf

As per this application note, there should be a minimum of 1 inch distance between PHY and Magnetics.

Do we have to follow this recommendation ?

Regards,

Harikrishnan T

Hi Harikrishnan,

Harikrishnan Thangamani said:

Can we place transformers on opposite sides of PCB (Same Location - Top and Bottom Layer) ?

Are you going to be routing one of the traces to the bottom for the transformer and then back to the top so that both traces are on the same layer for the connector?

.

Harikrishnan Thangamani said:

While I search for layout guidelines for Ethernet Interface, I found this application note from Pulse Electronics.

https://www.pulseelectronics.com/wp-content/uploads/2020/12/Pulse_Layout-Considerations-v7.pdf

As per this application note, there should be a minimum of 1 inch distance between PHY and Magnetics.

Do we have to follow this recommendation ?

We do not have this requirement. The total length of each MDI trace should be less than 2 inches, or 2000 mils. See this app note for more information: https://www.ti.com/lit/an/snla387/snla387.pdf?ts=1684776849250&ref_url=https%253A%252F%252Fwww.google.com%252F

Best regards,

Melissa

Hi Melissa,

I will attach the assumption on placement of PHY, Transformer and Connector.

The connector is not RJ45. PHY and Transformer highlighted in Violet Color means they are placed top and bottom (same location).

This is an assumption. Can we place like this ? Top Layer PHY to Top Layer Transformer same for bottom also.

Can I place like this ? I need clarification on Transformer placement alone.

I am moving the PHY in layout.

Regards,

Harikrishnan T

Hi Harikrishnan,

Placing the transformers on opposite sides of the board is not prohibited by our guidelines.

However, please make sure you are length matching your traces and accounting for cross talk and stubs. 

Best regards,

Melissa

Hi Melissa,

Thanks for your information on queries.

I have one more query on SMI Interface (Serial Management Interface).

As per IEEE 802.3-2022 Clause 22 Section 22.3.4, Delay between MDC and MDIO can be 0ns (Min) to 300ns (Max).

But in DP83869HM Datasheet Page No 16, MDC to MDIO delay was mentioned as 0ns (Min) to 10ns (Max).

Can you clarify why there is deviation from IEEE ? Is the above timing 10ns an error in datasheet ?

Regards,

Harikrishnan T