I am trying to run EtherCAT with a Sitara processor DP83826E.After following the TI app note "How and Why to Use the DP83826E for EtherCAT® Applications" ,page-7 . I am using the following code to write to the PHY Registers. However. my register dump, immediately after the write functions, differs from the App note. What is the reason behind that?
void dp83826WritePhyReg(uint32_t mdioBaseAddress, uint32_t phyNum)
{
CSL_MDIO_phyRegWrite(mdioBaseAddress, phyNum, 0x00, 0x3300);
CSL_MDIO_phyRegWrite(mdioBaseAddress, phyNum, 0x04, 0x01E1);
CSL_MDIO_phyRegWrite(mdioBaseAddress, phyNum, 0x09, 0x0020);
CSL_MDIO_phyRegWrite(mdioBaseAddress, phyNum, 0x0A, 0x0001);
CSL_MDIO_phyRegWrite(mdioBaseAddress, phyNum, 0x0B, 0x0008);
CSL_MDIO_phyRegWrite(mdioBaseAddress, phyNum, 0x18, 0x0080);
CSL_MDIO_phyRegWrite(mdioBaseAddress, phyNum, 0x19, 0x8020);
}