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TFP401: 3 questions about board design

Kazuki Ota
Prodigy 40 points
Part Number: TFP401
Other Parts Discussed in Thread: SN74LVC14A

I plan to use PanelLink Receiver in my design.
I chose TFP401 as a replacement for SiI1151[Silicon Image].

I have a few questions about designing the board.
I wasn't able to get a clear answer from the materials provided.
I would appreciate it if you could answer here.

1. When PDO#=LOW and in Output Drive Power Down Mode, is the state of the QE pin HIGH level, LOW level, or in an undefined state?
--- If it is in an undefined state, is it okay to connect a pull-down resistor to the QE pin? (To prevent malfunction of the input pin of the FPGA to which the QE pin is connected)

2. Is differential impedance control required for RX0+/-, RX1+/-, RX2+/-, RXC+/- traces?
--- If yes, what is the control value? Differential 50Ω?

3. What is the allowable trace length for output signals from the TFP401?
In the current situation where no measures are taken, it will be about 8 inches.
--- If I put a schmitt trigger (SN74LVC14A) in the output signal trace, is it right or wrong to put it in QE and ODCK?

  • 0
    TI__Guru**** 176631 points

    Hi,

    1. The TFP401/401A power down (PD = low) is a complete power down in that it powers down the digital core, the analog circuitry, and output drivers. All output drivers are placed into a Hi-Z state. All inputs are disabled except for the PD input.

    2. Differential impedance for  RX0+/-, RX1+/-, RX2+/-, RXC+/- will be 100ohm.

    3. The trace length of data and control signals out of the receiver should be kept as close to equal as possible. Trace separation should be ~5X Height. As a general rule, traces also should be less than 2.8 inches if possible.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 40 points

    Thank you for your prompt reply.

    1. What I want to know is the state of the output pin when PDO#=LOW, not when PD#=LOW. When PDO#=LOW, what is the level of the QE pin specifically, "H" or "L" or "undefined"?
    Also, what do you think about whether there is no problem with including a pull-down?

    2. I would like to control to 100Ω differential in my design as well. Is there a document that states that trace impedance control is required?

    3. The above contents have already been understood by reading the datasheet. Specifically, can you tell me whether the trace length of 8 inches seems to be a problem?
    Also, what do you think about whether there is no problem with inserting Schmitt triggers into QE and ODCK?

  • +1 in reply to Kazuki Ota
    TI__Guru**** 176631 points

    Hi,

    When PDO# = low, the output drivers (except SCDT and CTL1) are driven to a high-impedance state as well. Since the output is in a high-impedance state, why do you need to pull it down? 

    The differential impedance requirement is covered under the HDMI spec.

    How long you can drive the TFP401 output, and whether you can include Schmitt triggers depends on the setup and hold timing. You need to make sure you are not violating the setup and hold timing spec of the receiver.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 40 points

    Thank you for your prompt reply.

    The reason why I thought the pull-down was necessary was because I thought that the value of the input port on the receiver side (FPGA) would be undefined when QE=Hi-Z.
    I was inexperienced in how to handle Hi-Z input/output ports. I'm sorry.
    In an actual design, I would like to use the option function on the receiver side (FPGA) to enable/disable the device internal pull-down and confirm its usefulness.

    I understand differential impedance.

    Regarding the Schmitt trigger, I would check the specs on the receiver side (FPGA).

    Thank you very much for your answer.