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TCAN1146-Q1: TCAN1146 drives the bus to a dominant state if the CPU is reset while the TCAN1146 is in normal mode

Part Number: TCAN1146-Q1


Our design has an imx8mp CPU with its flexcan CAN controllers. When the tcan1146 is in first is put into normal mode and the CPU is then reset, there is a 3ms dominant 0 output on the CAN bus when the CPU tx pin drops to 0(I suspect). Is there a way to prevent this? VIO and VCC drops at reset but VSUP is kept. I was expecting tUVFLTR Under voltage detection delay time to kick in within from 3 to 50 µs according to the datasheet.

This is a rare case as this only happens on a hardware reset with button or hardware watchdog and normally we can take the tranceiver off bus in software.

  • Hi Mattias,

    Thanks for sharing this test result with us. 

    The dominant state on the CAN bus at system reset is consistent with the TXD pin going low while the transceiver remains powered. The resulting 3ms dominant period is the CAN driver interpreting the low signal on TXD as a dominant input before the internal dominant timeout causes the driver to return to the recessive state. In order to avoid this, the TXD signal can be supplied with an external pull-up to Vio so that the floating signal will be interpreted as a recessive signal when the system goes into reset. This pin-state is likely different during a hardware reset or watchdog reset and why this behavior is only observed during these conditions. 

    Do you know the state of the MCU driver pin for the TXD signal during/after the reset condition? Does the MCU drive this signal low (sink more current than an external pull-up can provide) or is it high impedance? Is this configurable? 

    During the reset event, what happens to the Vio and Vcc rails? If these voltage rails do not drop below their undervoltage threshold, the transceiver may remain in Normal mode for a longer period of time where it remains capable of driving a dominant on the bus. 

    Regards,
    Eric Schott