DP83822I: RX_SFD pulse sometimes changes to start of preamble

Alexander Ockert

Prodigy 70 points

Part Number: DP83822I

Hello,

I try to use the RX_SFD pulse as defined in chapter 8.3.3 of the Datasheet.

I use default values (0x5) in register 0x3f.

My measurements show that the RX_SFD pulse raises ca. 52 ns after SFD on RX path.

But sometimes, the pulse moves backwards to the start of the preamble, as shown here:

Can you explain why? I guess this is a malformed behaviour.

Best regards,

Alex

over 2 years ago

0 Alexander Ockert over 2 years ago

Prodigy 70 points

The given default values are for the PTP Receive and Transmit Timings

0 Gokul Koraganji over 2 years ago in reply to Alexander Ockert

TI__Mastermind 19250 points

Hi Alex,

I will try to recreate this in our local setup and see if the behavior exists in our setup too.

In the meanwhile, can you please check if you can see the same problem after programming 0x0456 = 0x000A.

Programming 0x0456[1] changes the source of SFD generation.

--
Regards,
Gokul.

0 Alexander Ockert over 2 years ago in reply to Gokul Koraganji

Prodigy 70 points

Hi Gokul,

after writing 0x456 with 0xa the RX_SOP pulse vanishes. There are no pulse generations at RX_SOP anymore.

This bit does not affect TX_SOP generation. These pulse are still generated.

Regards,

Alex

0 Alexander Ockert over 2 years ago in reply to Alexander Ockert

Prodigy 70 points

0x456=0x8 (default)

0x456=0xa

0 Gokul Koraganji over 2 years ago in reply to Alexander Ockert

TI__Mastermind 19250 points

Hi Alexander,

I can create the setup by Tuesday next week and keep you posted on the progress of debug.

--
Regards,
Gokul.

+1 Gokul Koraganji over 2 years ago in reply to Gokul Koraganji

TI__Mastermind 19250 points

Hi Alexander,

We tried with register settings 0x0456 = 0x000A, 0x04A0 = 0x1080.
With this we find that the SFD is flagged after a constant delay from preamble.

Can you please check at your end if this works for you?

--
Regards,
Gokul.

+1 Alexander Ockert over 2 years ago in reply to Gokul Koraganji

Prodigy 70 points

With settings 0x456[1]=1 (undocumented bit) and 0x4a0[7]=1 (enable WoL) it works properly.

Can you tell me what 0x456 bit 1 does? This bit is not described in datasheet.

0 Gokul Koraganji over 2 years ago in reply to Alexander Ockert

TI__Mastermind 19250 points

Hi Alexander,

PHY generates SFD in two different modules. Register 0x0456 selects which path to use.

Please see the block diagram below. Register 0x456 is the mux select in the block diagram.

Interface

Interface forum

DP83822I: RX_SFD pulse sometimes changes to start of preamble