Other Parts Discussed in Thread: DP83867IS
Hi.
I built custom board with 4 of the above PHY, which based on Xilinx ultrascle+.
I this design I have the processor with bunch of peripherals like spi, uart, ethernet..
Vivado assign address range in the address map [photo attached]
I want to build a test system that will check the validity of the pcb board connections of the ethernet channels.
Initially I thought about sw that will ping to some end point [For checking mechanism]
Then I saw in the datasheet BIST option - Built-in Self Test [page 35] which is simpler, more compact solution.
1. Are the registers of the PHY mapped to the address map of the MAC in Vivado design?
2. How I can achieve testing with BIST with the PHY registers?
Thanks!
