Part Number: TPD6E05U06
Customer feedback that the USB3.0 requirements cannot be met when using this product。
Do we have the related SI mode of high speed test?
Or any other experiment results?
Which could convince customers that this is not our device's problem.
Hi Fabio,
We have eye diagrams of a 6 Gbps HDMI signal through this device:
USB3.0 should have a max data rate of 5Gbps so this device can definitely support that signal speed.
Did the customer have issues with this device on their board?
Many factors such as trace length and other components on the line will add capacitance that could bring the system out of compliance.
Regards,
Sebastian
They just said; If no our device the test result is good.
If our device on the board, it is bad and the impedance cannot meet the requirements of USB3.0, as the picture shows.
Adding the comment from customers:
"Can you provide us with the SI model and test data? The specification includes testing high-frequency parameters. So there should be SI model and related test information."
The customer focus on the impedance, not the diagram.
1. Is the S model downloaded simulated or measured data?
The abscissa of this data domain is a log model rather than a linear model. The impedance derived from this data is inaccurate, but it is clear that the impedance has a low point.
2. Can you provide the linear S model or impedance test results (according to USB3.0 standard test results) shown in the following products (PN: TPD6E05U06RVZR)?
Now they focus on impedance metrics, not eye diagrams or IL.
3. The impedance specification of the USB3.0 association is 90+/-15 ohms. Therefore, if this requirement cannot be met, the product can be considered as substandard.
The impedance plot below is the impedance comparison between the PCBA w ESD (red trace) and the one w/o ESD (black trace). It indicates that the PCB trace w/o ESD is about 90 ohms. The impedance drops about 20 ohms when the ESD attached.
The picture below is the ESD footprint and the voids underneath it. As shown in the PCB stackup below, the PCB has 6 layers. The ESDs are attached on the bottom side.
Except for optimizing the PCB layout, the customer also wants to know the impedance performance of the ESD itself. If the ESD’s impedance is too low, the high impedance of the PCB can be pulled low by the ESD.
Hi Fabio,
Apologies for the delay, below are the simulation results. I'm not seeing a drop of 20 Ohms in my simulations but the trace characteristics from the customer board will affect impedance results differently.
Regards,
Sebastian
