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TSB41BA3A: TSB41BA3A

kerry querns
Prodigy 120 points

Part Number: TSB41BA3A

Need clarification

Datasheet pg 18 states JC of 0.17 C/W with bottom soldered to pad on board

Also state 0.17 C/W if the bottom is not soldered to board

Doesn't seem to make sense that they are the same.  Is the JC for both to the metal pad on the base or the leads, and 

is the grounding scheme on page 28 required for the TPFPEP version of the device.

Data also say JC valid on "High conductivity Texas Instruments recommended test board" but doesn't clearly define.  I assume

themal pad on board for both the places this is defined, but does it require 2 oz copper in the board?  Deissipation Rating Table on 

page 15 mentions 2 oz "traces" for these configurations but traces are usually exterior layers of bd

  • 0
    TI__Guru**** 177141 points

    Hi,

    For the question on the 2 oz copper, please refer to this app note, https://www.ti.com/lit/an/slma002h/slma002h.pdf, in particular section A.4 Texas Instruments Example Jedec Board Design for PowerPADTm Packages.

    For the question on the theta JC, please refer to this app note, https://www.ti.com/lit/an/spra953c/spra953c.pdf.

    The grounding scheme on page 28 is not tied to a specific device. The RC circuit is used to reduce EMI, 

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 120 points

    Section A.4 figure would indicate the board is essentially copper? Like, the ground plane and power plane add up to the total board thickness, so likely there is an error here. And do you have a specific location I should be looking at in spra953c ... I don't really see anything clarifying why the 0.17 is valid for soldered or unsoldered to board. 

  • 0 in reply to kerry querns
    TI__Guru**** 177141 points

    Hi,

    70%–95% of the power generated by the chip is dissipated from the test board, not from the surfaces of the package. So there is very little heat transfer on the top of the package, and this is why you see the Theta JC is the same between the two device soldering conditions.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 120 points

    David, there multiple paths to the board but the primary ... if you solder ... is through the soldered pad.  If you do not solder then the heat has to to go through the leads to the board and via convection/gaseous conduction off the bottom of the device to the board.  Anyhoo, no way the JC is the same whether soldered or unsoldered (unless this was one of your lead frame devices, and even then not likely the same. 

  • 0 in reply to kerry querns
    TI__Guru**** 177141 points

    Hi,

    The junction-to-case thermal resistance metric was originally devised to allow estimation of the thermal performance of a package when a heat sink was attached. EIA/JESD51-1 states that RθJC is, “the thermal resistance from the operating portion of a semiconductor device to outside surface of the package (case) closest to the chip mounting area when that same surface is properly heat sunk so as to minimize temperature variation across that surface.”

    You can also see section 2 of this app note for more detail on the RθJC measurement, https://www.ti.com/lit/an/spra953c/spra953c.pdf.

    Thanks

    David