Part Number: DP83822HF
Hi,
Good Day.
Pin TX_CLK mode output in the state during reset and RGMII mode :
Customer's sequence:
- First: In reset mode (pin reset_n in low for a low during and the pin return in high), this pin "TX_CLK" is configurated in output mode (picture 1).
- His understanding: into during the reset mode, the pin TX_CLK, on the PHY, is configuring on output. and the pin connected to the MAC also (picture 2).
His question :
- Do you think this is a problem? If yes, do you have a solution for him?
Also, he thought of a solution: could you answer the question?
- What is the logic level for TX_clk PHY (Low or High)?
Please advise. Thank you very much.
Best Regards,
Ray Vincent
