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TLK10232: Refclk at power-up.

Peter Palaiologos
Prodigy 40 points
Part Number: TLK10232

Hello

In my TLK10232 design I have noticed something that could be a coincidence or might mean something: When the Refclk input is driven by a steady CO, the phy is working and traffic flows. When Refclk is driven by a clock coming from an FPGA or a DPLL, the phy is not working (there are continuous data errors). I have measured the clock input in all cases, all clocks are fine. The difference is that problems occur when the clock is not present immediately after power-up (both the DPLL and FPGA are configured with a significant delay after power up). However, in all cases, Reset goes up after the clock has been applied. So could the power-up clock delay cause such problems?

  • 0
    TI__Mastermind 20747 points

    Hi Peter,

    I would not expect any issues with the power up clock delay causing issues since the device is held in reset.  Perhaps one way to confirm this though is would it be possible to delay the CO signal similar to refclk from FPGA and see if you observe the same behavior?

    Do you have any scope captures of the clocks you might be able to share?

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 40 points

    Hello

    This is the 'P' signal, the 'N' is similar.

    I used a passive 1:10 scope, so the true signal is 100mV / division (not 10 mV as shown). Hence the differential is more than 400mV p-p.

    The signal driver has programmable amplitude, we also tried wider signals but we saw no difference.

    We also checked for jitter, wander etc. with a spectrum analyzer, we found the frequency steady.

    Looks OK to me.

  • 0 in reply to Peter Palaiologos
    TI__Mastermind 20747 points

    Hi Peter,

    Thanks for sharing.  Is the expected frequency of this clock 156.25?  Can you confirm that you have observed this?  Additionally, can you confirm that the random jitter of the clock is <1ps?

    Thanks,
    Drew