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TS3DV642-Q1: TS3DV642-Q1

GOVIND S
Prodigy 120 points
Part Number: TS3DV642-Q1

Hi Team,
In one of our latest project we are using TS3DV642-Q1 for high speed CSI MIPI (1.6GbpS).
Our aim is to guide MIPI signals from 6 different cameras to a particular MIPI port of processor by switching each cameras one by one.
Please find the attached Architecture.
What are the possible disadvantage of using this mux architecture?
Our MIPI data speed is 1.6Gbps, does using three MUXs serial to pass these signals will reduce the net data rate capabilities. Please explain.

  • 0
    TI__Guru**** 177031 points

    Hi,

    Cascading multiple MUX in series is going to degrade the bandwidth.

    The MUX 3dB cut off frequency can be calculated using the below formula, 

    RL = Loading resistance

    Ron = Resistance between the source and the drain terminal when the MUX is closed or ON

    CD = Drain capacitance

    CL = Load capacitance

    Each cascading mux adds more MUX resistance and capacitance. Layout and other sources of capacitance (layout, loading conditions of the multiplexer) will degrade the signal further as more capacitance on the bus will also reduce the BW. 

    Physically you can cascading three TS3DV642-Q1 together, but I do not have the BW of cascading three TS3DV642-Q1 since the BW will vary depending on the system design.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 120 points

    Thank you David for the reply.