DP83867IS: How to provide Xilinx MAC mgt_clk from the PHY

Hi,

I am working on ethernet project on Xilinx Ultrascale+ which consists of the following:

TI dp83867is that is connected to AXI ethernet subsystem IP.

My design works at SGMII, 100Base-tx configuration.

in AXI ethernet subsystem I need to provide 125MHz clock mgt_clk that is routed from one of the quad transceivers.

From the PHY I have 625MHz differential clock [SGMII_COP,SGMII_CON]

is it possible to divide that clock to achieve 125mhz? 

or do you have other suggestion for 125mhz from the PHY to Xilinx MAC?

I can add external differetial  125mhz clock to the the board, but if I have one in the PHY, I prefer to use it.