SN65DSI86: Can sn65dsi86 support panel with the following parameters?

Vertical Blanking=1848

Vertical front porch=8

Vertical sync width=8

Vertical back porch=1832

Horizontal Blanking=100

Horizontal front porch=32

Horizontal sync width=8

Horizontal back porch=60

frame=60Hz

RGB888

dual dsi

Width=2880

Height=1800

Please help confirm,Thanks!

Hi Chen,

DSI86 can only support data rates up to 5.4Gbps. It looks like this panel runs at 8.1Gbps, which the DSI86 cannot support.

Thanks, Allison

Hi Allison,

Maybe this is the 120Hz refresh rate, but we're only using 60Hz.

1. If the MIPI DSI rate is 4Gbps, how to calculate the eDP rate?
2. Does sn65dsi86 support the above panel parameters?

Hi Chen,

Typically, the eDP rate is fixed. We calculate the DSI rate by following the formulas in the DSI86 Programming Guide here: https://www.ti.com/lit/an/slla425/slla425.pdf 

Given the above panel parameters, please note the below calculations:

Display pixel clock frequency = Htotal x Vtotal x refresh rate = 311MHz

Stream bit rate = pixel clock x 24bpp = 7GHz

Min required DSI clock frequency = stream bit rate / (2 x # of DSI lanes) = 460MHz (assuming 8 DSI lanes)

The DSI86 max DSI clock frequency is 750MHz. The DSI86 can support this panel as long as the refresh rate is 60Hz and the eDP speed does not exceed 5.4Gbps.

Thanks, Allison

Hi Allison,

For qualcomm platform, dual dsi means Width=1440 and lane=4 for a dsi.

1. calculations

   pixel clock = Htotal x Vtotal x refresh = (1440+60+32+8)*(1800+1832+8+8)*60 = 337075200 , so pixel clock = 337MHz

   bit clock = (Hactive + HBP + HFP + HSW) * (Vactive + VBP + VFP + VSW) * refresh * total bit per pixel / total lane num,

   so, bit clock = (1440+60+32+8)*(1800+1832+8+8)*60*24/4=2022451200, bit clock = 2022.45MHz

   dsi clock = bit clock / 2 = 1011.23MHz, one lane of a dsi was over 750MHz

   My calculations are consistent with the qualcomm spreadsheet, and my calculations show that sn65dsi86 does not support this panel.

2. register

In the datasheet P48-P49, 0x36 is CHA_VERTICAL_BACK_PORCH(7:0), the max value of this register is 255, but the Vbp of the panel is 1832, over 255.

So the Vbp parameter off this panel is not supported?

80-NH713-1_U_DSI_Timing_Parameters_TM050JVHN12(1).xlsm

Hi Chen,

Correct, the DSI86 will not support this panel if the DSI clock requires a frequency of 1011.23 MHz. 

DSI86 cannot support a VBP of 1832 lines.

Thanks, Allison 

Hi Allison,

If the DSI clk frequency is 1011.23MHz, how do I calculate the eDP rate?