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DS90UB941AS-Q1: Register report conflicting

Nuri Seko
Prodigy 160 points
Part Number: DS90UB941AS-Q1

Hello Team!

Hope this query finds you well!

While working with the serializer DS90UB941AS-Q1, we have noticed that when the register 0x20(DSI_CONFIG_0) was set to disable the VC (bit 6 = 1), and the register 0x23(DSI_ERR_CFG_1) was set to disable invalid VC errors on DSI_ERR_STATUS(bit 3 = 0), we still get an invalid VC error on DSI_ERR_STATUS(bit 4 = 1).(all indirect registers)

Also on the direct register side we also have the register 0x0C(GENERAL_STS) giving us no indication of any errors on the DSI.

We are also getting a black screen on the display, and we're wondering whether this discreptancy is related to that.

Thank you in advance,

Nuri

  • 0
    TI__Mastermind 25765 points

    Hi Nuri,

    Thanks for you question.

    Can you provide a reg dump of the main registers as well as the DSI registers so I can see the full context?

    Nuri Seko said:
    We are also getting a black screen on the display, and we're wondering whether this discreptancy is related to that.

    Does the black screen only happen with end-to-end video (DSI input) or is there a black screen with patgen as well? Has there been lock established with the DES?

    Regards,

    Ben

  • 0 in reply to Ben Dattilo
    Prodigy 160 points

    Hello Ben,

    Thank you for your feedback!

    In regards to the registers our software colleague is preparing the script to get the register dump on the main registers at the moment. I will post it here as soon as it is ready.

    As for the black screen of the display, we followed the chart and we've been successful on the green ticked parts but not successful on he non ticked parts:

    Hopefully this chart helps in clarifying. Also the DSI and pixel clock are correct based on our calculations and on the physical sample. The timings were based on the read Pixel clock too, so we don't see why we're facing an issue in this case.

    Thank you in advance!

    Nuri Seko

  • 0 in reply to Nuri Seko
    TI__Mastermind 25765 points

    Hi Nuri,

    Thanks! This chart is helpful. Can you go ahead and check for periodic LP-11 transitions, even though the data type was reported correctly? The "x" by the packet timing - does this mean you are not able to check the DSI packet timing, or the DSI packet timing is incorrect?

    Regards,

    Ben

  • 0 in reply to Ben Dattilo
    Prodigy 160 points

    Hello Ben,

    Yes, the periodic LP-11 is appearing approximately every frame(detected in the oscillosope as shown in the debugging guide, and the time between 2 LP-11 is about the time it takes for 1 frame. We also see the sync signals in the end of each line calculated by the expected frequency of every line. We don't get any DSI errors, so clock seems okay too. We're having a bit of trouble understanding as to why we have a black screen. Do you have any suggestions about the situation?

    Thank you in advance!

    Nuri

  • 0 in reply to Nuri Seko
    TI__Mastermind 25765 points

    Hi Nuri,

    What mode is the DSI source in? Burst mode, non-burst mode with sync pulses, or non-burst mode with sync events? Also, the register (main registers as well as indirect DSI registers) dump would be helpful when available. 

    Also, does black screen occur all the time or only sometimes?

    Regards,

    Ben