SN65DSI84: Still flickering issue

Hi Zach,

For your information, I measured the timing between the steps of the initialization:

Step 3 to 4:  >10ms

Step 4 to 5: ~= 24ms

Step 5 to 6: NA

Step 6 to 7: ~= 29ms

Step 7 to 8: ~= 66ms

Thanks,

Charles

Hi Charles, 

If you clear the register 0xE5 by writing 0xFF after power up, and then read the register again, are you seeing any bit in register 0xE5 being set? This is step 10 to 11 in the initialization sequence.

Thanks, Allison

Hi Allison,

Yes after writting 0xFF on register 0xE5, I see the "PLL UNLOCK" error set again ...

How can I fix the issue ? Only by restarting the initialization ? Do you know where could be the root cause ?

Thanks,

Charles

Hi Charles,

Can you measure the line time on the DSI input? You can refer to this FAQ to help with this measurement: https://e2e.ti.com/support/interface-group/interface/f/interface-forum/990480/faq-sn65dsi84-how-to-debug-flickering-video-with-sn65dsi83-sn65dsi84-and-sn65dsi85

Line time = Htotal / LVDS Clock = 1440 / 72MHz = 20us. Can you ensure you're seeing a 20us line time?

Thanks, Allison

Hi Allison,

Our horizontal field is 823 and not 1440, our screen is in Portrait mode.

So the line time = 823 / 72 =~ 11,4µs ==> With the oscilloscope I have line time =~ 11,5µs 

About my register error, How can I delete and fix PLL UNLOCK error ?

Thank you

Best regards,

Charles

For your information, I discussed with Zach on these tickets : 

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1199319/sn65dsi84-flickering-issue/4549920?tisearch=e2e-sitesearch&keymatch=SN65DSI84%252520issue#4549920

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1222217/sn65dsi84-blue-cyan-issue?tisearch=e2e-sitesearch&keymatch=SN65DSI84%20pll%20fix%20error#

Thanks,

Charles

Also for your information

I did eye diagram on DSI (closest to DSI input bridge) and LVDS clock (closest to LCD panel).

#DSI CLK:

#LVDS CLK:

Thanks,

Charles

Hi Charles,

Can you zoom in on the DSI clock after you tie EN to high when you take this scope shot? What is the frequency of the clock right after you tie EN to high?

With the line time being matched between the DSI input and the LVDS output, the flicking issue may not come from line time mismatching. Can you please change to a reference clock? An excessively noisy DSI CLK may lead to an unstable LVDS clock output, and this might be the reason why you are seeing issues. If you are unable to use a reference clock, can you share the layout of the system?

Thanks, Allison

Hi Allison,

I took a scop shot when EN pin tied to high:

About the layout, I need to discuss internally before to send you.

Do you have a e-mail or private space to share with you ? Or via our FAE contact ?

Best Regards,

Charles

Hi Charles,

It looks like the clock transitions to HS mode while the EN pin is still ramping up. Is there a way you can shift the HS mode of the clock to occur before EN begins ramping? You can also add a pull down capacitor to the EN pin to delay the ramp. 

Can you also try toggling the PLL_EN bit when you see the flickering? 

Best, Allison

Hi Allison,

You mean that DSI clock should not be in transition when the EN pin is going to High state ?

However, the LP11 mode is established well before the EN pin high state

Below the EN pin goes low then high while init :

Thanks,

Charles

Hi Allison,

When I toggle the PLL_EN bit while the flickering appears, the register is still equal to 0x01

Best Regards,

Charles

Hi Charles,

In the first scope shot above, channel 3 seems to be a DSI data lane, which should be in LP11 mode while the EN pin is going to high state. This is the correct configuration for the data lane. Channel 4 is the DSI clock lane that I am referring to.

Please see the scope shot below. The clock (channel 1) transitions to HS mode while the EN pin (channel 2) is ramping to high. The DSI clock should already be in HS mode before EN goes from low to high. Can you shift the DSI clock so that the HS mode occurs before EN begins ramping from low to high?

Does the flickering stop when you toggle the PLL_EN bit?

Thanks, Allison

Hi Allison,

We will try it, about the DSI clock.

and yes, when I toggle the PLL_EN, the flickering stop

Thanks,

Charles

Hi Allison,

I tried with a 1µF on Enable pin of the bridge, and there are still flickering.

The Enable pin and the DSI clock are the same on oscilloscope than previous one.

On the picture below, the DSI clock didn't shift from 2 differents mode, but only does a simple transition because of the output comes from high impedance when the enable pin is at low state:

Do you have a new way yo solve the issue please ?

Thanks,

Charles

Hi Charles,

You mentioned that the flickering stops when you toggle the PLL_EN bit. After you toggle this bit, can you clear register 0xE5 by writing 0xFF and then read the register? Can you also read register 0x0A and ensure the PLL_EN_STAT bit is set to 1?

Thanks, Allison 

Hi Allison,

After I toggle the PLL_EN bit and clear the 0xE5 register, the value of the register 0xE5 always equals 0x01.

And also the PLL_EN_STAT bit is still set to 1.

However, I tried 3 times, and sometimes, when I toglle the PLL_EN bit the flickering disappears and sometimes not (I need 2 toggles to delete the flickering).

Thanks,

Charles

Hi Charles,

I understand you do not have a way to implement a reference clock, but the issue seems to be stemming from the DSI input clock. Is there any way you can implement a clean reference clock as a way to rule out the DSI clock being the root cause? Otherwise, you might need to toggle the PLL_EN bit until the flickering disappears in order to fix your issue.

Thanks, Allison

Hi Allison,

In fact, we can integrate a external reference clock but we designed with a wrong oscillator ref (SG-210). I mean, it doesn't respect the Ti specification for the fall/rise times.

From Ti datasheet:

From our external ref clock datasheet: (SG-210)

The Rise/Fall times is around 3ns and not 1ns ... So it can't be possible with this one, and I can't change footprint. Any other ref can acheive this requiement.

Is it critical the rise/fall times ? Because I already try and we still got flickering ...

Thanks,

Charles

Hi Charles,

Can you send me your layout in Allegro format? I sent you a friend request, so you can send it to me privately.

Thanks, Allison