• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 32 subscribers
  • Views 109 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83825I: XI input, floating during 40msec

Oba
Genius 16010 points
Part Number: DP83825I

Hello,

 

My customer built their prototype using DP83825I and is evaluating the board.

Then they want to confirm one thing.

 

DP83825I XI input is clocked by the external 25MHz clock generated by the FPGA on the board.

After powering up, they can see about 1.0V on XI input pin before the FPGA start to output the 25MHz clock.

The time between the power up and FPGA clock output start timing is about 40msec. It means XI input is floating during 40msec after powering up and they can see about 1.0V on the pin.

They can see the same 1.0V when removing the FPGA.

 

They just want to confirm if this situation, seeing around 1.0V on XI input pin during about 40msec, is no problem.

Is it no problem? Or does they need to add an external pull-up or down or something else termination?

 

Regards,

Oba

  • 0
    TI__Expert 8640 points

    Hi Oba,

    Oba said:
    It means XI input is floating during 40msec after powering up and they can see about 1.0V on the pin.

    The recommendation is that clock should be available at power ramp, else additional RESET_N is needed.

    Is customer facing any communication or PHY issues ?

    What VDDIO is being supplied to the PHY ? and what is the default state of FPGA pin supplying clockout ?

    Regards,
    Rahul

  • 0 in reply to Rahul
    TI__Genius 16010 points

    Hello Rahul,

    Thanks for your reply.

    They uses REST_N and it is asserted (LOW) until FPGA starts to output the clock.
    During this 40mV, the FPGA clock out pin is Hi-Z.
    VDDIO is 3.3V.
    They don't see any issue as of now.
    Thuy just want to confirm if this condition could causes a possible.

    They are going to make their next prototype soon.
    So they can modify the boad like adding pull-up/down if this condition has a problem.

    Regards,
    Oba

  • +1 in reply to Oba
    TI__Expert 8640 points

    Hi Oba,

    As long as reset line is held and the XI supply is available before releasing reset of the PHY, this shouldn't cause any issue.

    Regards,
    Rahul