DP83TG720S-Q1: BCI issue & Verilog model

Here are 2 more questions on DP83TC720S-Q1, Do you mind helping to have a view on them?

• Recently my customer met BCI-LINKDOWN issue on DP83TC720S issues and want to get our guidance. my customer is refer to the standard, ISO11452-4. Please help to have a view on below questions firstly, if necessary, my customer would like to have on-line meeting to discuss with us.

1. BCI 200mA test linkdown（Marvell PHY will not happen）
2. Under master mode，inject interference in linkup status, linikdown happen，PHY can not send send-S signal as expectations.
3. Under master mode，inject interference in non-linkup status, linikdown happen，PHY can send send-S signal. The opto feedback send_S signal，but link still can not be set up.
4. in ESD power-up mode，linkdown happen.（Marvell PHY will not happen）
5. The pre-stage of the common mode inductor adds an TVS. Is it necessary to add TVS again between paths of PHY and common mode inductor?  I remember there is a clamping inside of our PHY right?

• my customer is designing the PHY GMAC controller of DP83TG720S-Q2. They need PHY simulation document to make sure the controller can work as normal. Can we provide Verilog Model of DP83TG720S-Q2 (encryption version is also ok)?

Best regards,

wenting