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SN65DSI86: SCH check

Part Number: SN65DSI86
Other Parts Discussed in Thread: , TEST2

Hi team.

About the REFCLK,
1. this frequency is defined by GPIO[3:1], there are 12 MHz, 19.2 MHz, 26 MHz, 27 MHz, and 38.4 MHz. Optional, how to choose, whether the screen and main control chip corresponding to different frequencies request? 2. This pin is connected to the host control terminal, what are the specific requirements for the pins of the host control terminal? Can any GPIO port meet the requirements?

Could you pls help to check the sch? Thanks a lot!

Thanks!

Rayna

  • Hi Rayna,

    1. For REFCLK, please refer to Section 8.3.3.1 in the SN65DSI86 datasheet.

    2. Can you clarify what you mean by host control terminal? The REFCLK pin should be tied to an external oscillator, similar to the CDC on the SN65DSI86EVM.

    Thanks, Allison

  • Hi Noe,

    for second question, customer want to use MCU GPIO to generate a clock signal, so they want to confirm the spec requirement.

    For schematics, is there any mistake? 

    Thanks!

    Rayna

  • Hi Rayna,

    The REFCLK signal just needs to meet the specifications outlined in section 7.7 of the datasheet. Please refer to below for REFCLK requirements:

    For the schematic, it is recommended for the TEST2 pin to be pulled up to Vccio in case there is a need for DP compliance testing. It is also recommended to use source detection pull-up and pull-down resistors on the AUX pins, as shown below:

    Thanks, Allison