DS90UB947-Q1: The clock input 947 will pull down 30ms

Hey Yao,

Thanks for the information. Is this happening on a single system or multiple what is the background on this issue?

Yao YunXuan said:

1:The clock pull down how many times will cause 947/948 error?

Every single time you have CLK loss it will corrupt the FPD-Link signal. When CLK is pulled down, your PCLK is disrupted which will temporarily disrupt the FPD-Link connection. Any time PCLK is changed, it is recommended to digital reset the SER and DES afterwards to make sure the locking/AEQ is deterministic.

Yao YunXuan said:

2:If error orrur, whether we can detece it?

Link status can be monitored on 947 in register 0x0C[0] or by reading the remote deserializer LOCK status.

• Check register (0x0C) on 947 bit0 is link status 
• Check register (0x1C) on  948 bit0 is lock status 

Yao YunXuan said:

3:If error orrur, whether we can reset it by write some reg?

You can try doing a digital reset of the Des (948) first to see if that is sufficient to recover the CLK 

• on 948 Write 0x5 to register 0x1

If a digital reset to the Des doesn't recover the CLK then you may have to do a digital reset to the Ser as well in case your data/clk are out of sync. 

• On 947 Write 0x1 to register 0x1

Regards,
Fadi A.

Hi Fadi,

Thanks for you reply, but we still did not fix this issue.

Below is our block diagram, when we switch the video signal input to 86175 between the 934(use for 360 panorama) and soc, 

the CLK which input to 947 will pulled down almost 30ms, in this time the lock signal is always at high level,

but the panel display is error.

Can you give me any suggestions about this? Is it cause by 947?

And this is the reg data of 947 and 948.

Hi Fadi,

We had already make sure this issue caused by 947, because it can be resume if we reset the 947.