Other Parts Discussed in Thread: ALP
Hi team,
Could you help check this register configuration? The customer also find the CLK is not their expectation. They hope the CLK is 70M by 2 frequency division. But actually they test the clk is 35M and the display does not work. And this is a new issue and not related to any other previous question. Thanks in advance.
uint8_t Test_0x66_03[2] = {0x66,0x03};
uint8_t Test_0x67_03[2] = {0x67,0x02};
uint8_t Test_0x66_04[2] = {0x66,0x04}; //设置总帧大小2064 760
uint8_t Test_0x67_04[2] = {0x67,0x10};
uint8_t Test_0x66_05[2] = {0x66,0x05};
uint8_t Test_0x67_05[2] = {0x67,0x88};
uint8_t Test_0x66_06[2] = {0x66,0x06};
uint8_t Test_0x67_06[2] = {0x67,0x2F};
uint8_t Test_0x66_07[2] = {0x66,0x07}; //设置像素1920 720
uint8_t Test_0x67_07[2] = {0x67,0x80};
uint8_t Test_0x66_08[2] = {0x66,0x08};
uint8_t Test_0x67_08[2] = {0x67,0x07};
uint8_t Test_0x66_09[2] = {0x66,0x09};
uint8_t Test_0x67_09[2] = {0x67,0x2D};
uint8_t Test_0x66_0A[2] = {0x66,0x0A}; //同步宽度 hsw 50 vsw 10
uint8_t Test_0x67_0A[2] = {0x67,0x32};
uint8_t Test_0x66_0B[2] = {0x66,0x0b};
uint8_t Test_0x67_0B[2] = {0x67,0x0A};
uint8_t Test_0x66_0C[2] = {0x66,0x0c}; //设置后沿 30 20
uint8_t Test_0x67_0C[2] = {0x67,0x1E};
uint8_t Test_0x66_0D[2] = {0x66,0x0d};
uint8_t Test_0x67_0D[2] = {0x67,0x14};
uint8_t Test_0x66_0E[2] = {0x66,0x0E};
uint8_t Test_0x67_0E[2] = {0x67,0x00};
#if 1
uint8_t Test_0x65_0[2] = {0x65,0x07}; //内部时钟
uint8_t Test_0x64_0[2] = {0x64,0x37};
#else
uint8_t Test_0x65_0[2] = {0x65,0x08}; //外部时钟
uint8_t Test_0x64_0[2] = {0x64,0x37};
#endif
uint8_t Test_0x63_0[2] = {0x63,0x01};
uint8_t Test_0x34_0[2] = {0x34,0x11};
通过硬件IIC往948里面写数据，数据如下：
case 0:IICA0_MasterSend(IICA0_948_ADDR, Test_0x66_03, 2,10);break;
case 1:IICA0_MasterSend(IICA0_948_ADDR, Test_0x67_03, 2,10);break;
case 2:IICA0_MasterSend(IICA0_948_ADDR, Test_0x66_07, 2,10);break;
case 3:IICA0_MasterSend(IICA0_948_ADDR, Test_0x67_07, 2,10);break;
case 4:IICA0_MasterSend(IICA0_948_ADDR, Test_0x66_08, 2,10);break;
case 5:IICA0_MasterSend(IICA0_948_ADDR, Test_0x67_08, 2,10);break;
case 6:IICA0_MasterSend(IICA0_948_ADDR, Test_0x66_09, 2,10);break;
case 7:IICA0_MasterSend(IICA0_948_ADDR, Test_0x67_09, 2,10);break;
case 8: IICA0_MasterSend(IICA0_948_ADDR, Test_0x66_04, 2,10);break;
case 9: IICA0_MasterSend(IICA0_948_ADDR, Test_0x67_04, 2,10);break;
case 10:IICA0_MasterSend(IICA0_948_ADDR, Test_0x66_05, 2,10);break;
case 11:IICA0_MasterSend(IICA0_948_ADDR, Test_0x67_05, 2,10);break;
case 12:IICA0_MasterSend(IICA0_948_ADDR, Test_0x66_06, 2,10);break;
case 13:IICA0_MasterSend(IICA0_948_ADDR, Test_0x67_06, 2,10);break;
case 14:IICA0_MasterSend(IICA0_948_ADDR, Test_0x66_0C, 2,10);break;
case 15:IICA0_MasterSend(IICA0_948_ADDR, Test_0x67_0C, 2,10);break;
case 16:IICA0_MasterSend(IICA0_948_ADDR, Test_0x66_0D, 2,10);break;
case 17:IICA0_MasterSend(IICA0_948_ADDR, Test_0x67_0D, 2,10);break;
case 18:IICA0_MasterSend(IICA0_948_ADDR, Test_0x66_0A, 2,10);break;
case 19:IICA0_MasterSend(IICA0_948_ADDR, Test_0x67_0A, 2,10);break;
case 20:IICA0_MasterSend(IICA0_948_ADDR, Test_0x66_0B, 2,10);break;
case 21:IICA0_MasterSend(IICA0_948_ADDR, Test_0x67_0B, 2,10);break;
case 22:IICA0_MasterSend(IICA0_948_ADDR, Test_0x66_0E, 2,10);break;
case 23:IICA0_MasterSend(IICA0_948_ADDR, Test_0x67_0E, 2,10);break;
case 24:IICA0_MasterSend(IICA0_948_ADDR, Test_0x63_0, 2,10);break;
case 25:IICA0_MasterSend(IICA0_948_ADDR, Test_0x34_0, 2,10);break;
case 30:IICA0_MasterSend(IICA0_948_ADDR, Test_0x65_0, 2,10);break;
case 31:IICA0_MasterSend(IICA0_948_ADDR, Test_0x64_0, 2,10);break;
