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DP83869HM: RESET_N pin

Ivan Mazur
Prodigy 20 points
Part Number: DP83869HM

Hi support team!

Im using the DP83869HM, project in design stage and i want to clarify some points about RESET_N pin.

It is clear that RESET_N shall be held low for minimum 200ms after the last supply power up.

In my design PHY part will be started automatically and uP won't be able to control it, so i want to use the option proposed in DS (simple RC curciut). But im confused about RESET_N pull-up inside the IC.

In the DS, table 7-1 RESET_N pin type is not PU, its just empty, but in the tables 7-2, 7-3, 7-4 i can see that the pin is PU or PD.

So there are the questions:

1)  Is there a pull for RESET_N pin inside the chip? If so, what the purpose of external 100Ohm in RC curciut? Current will be limited more by internal pull up, because it weak i guess

2) If so, does RESET_N pull type depends on mode used?

3) What the inside pull-up typ. resistance value?

Thanks in advance, 

Ivan

  • 0
    TI__Mastermind 19250 points

    Hi Ivan,

    I'll check on PD on RESET_N with our team. From my understanding RESET_N is PU always.

    RESET_N has a pull up of 9kohms and hence 100ohm makes it slower for the 9kohm pull up to pull the pin to VDDIO after power-up.

    --
    Regards,
    Gokul.

  • +1 in reply to Gokul Koraganji
    TI__Mastermind 19250 points

    Hi Ivan,

    I checked with our design and can confirm that RESET_N is PU always.

    I will work with our team to get datasheet updated.

    --
    Regards,
    Gokul.

  • 0 in reply to Gokul Koraganji
    Prodigy 20 points

    hi Gokul, thanks! Could ypu help with another questions?
    1) as i understood 100Ohm (or another small resistance) shall be placed to limit the cap discharge current when the source will pull line to 0
    2) i made some calculations with the 9k pull-up + 100Ohm + 47uF cap and im not sure that the 47uF is enough. Im using the 1V8 VDDIO, so the VIL max is 0.35*1.8V = 0.63V. After the 200ms the voltage will be 680mV approx (for ideally components, if we using ceramic cap it will be higher because capacity is degraded due to the bias applied). If we are using 63uF we will have 540mV approx. 
    But im worried about the RESET_N line voltage skew, its very slow. Can this affect the behavior of the internal logic when the voltage is near the VIH min value (switching to and from the reset state several times)?
    3) In the DS I can see that the RX_D3, RX_D2 pins are PD, can you confirm that for the RGMII to 1000Base-X mode i dont need to put any additional PDs on these pins?

  • 0 in reply to Ivan Mazur
    TI__Mastermind 19250 points

    Hi Ivan,

    Regarding the capacitor on RESET_N line, I understand that you have calculated the cap for 200ms delay. But, there are design margins in 200ms (wait time or power-on reset time) and VIL of the device.
    47uF cap is selected based on design simulation where margins and interdependencies are taken into account. So, 47uF should be sufficient. Higher cap will not degrade the performance.
    The RESET_N receiver inside the PHY has in-buit hysteresis (around 20mV) to take care of the slow ramp causing glitches inside the PHY. So, it should be safe even if RESET_N ramp is slow.

    Ivan Mazur said:
    3) In the DS I can see that the RX_D3, RX_D2 pins are PD, can you confirm that for the RGMII to 1000Base-X mode i dont need to put any additional PDs on these pins?

    No external pull downs are needed on RX_D2 and RX_D3.

    --
    Regards.
    Gokul.