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Original question:

TCA9548A: TCA9548A: Design help

TCA9548A: Recommended current required on VCC

Trushal Alshi
Prodigy 140 points
Part Number: TCA9548A


We are designing pcb for TCA9548A. My question is regarding maximum operating current sunk from VCC pin.

The datasheet  suggests ICC to be max up to 20 uA (for 2.7V VCC) in operating mode and ΔICC to max 20 uA.

I did not understand meaning of ΔICC from datasheet. Should the maximum operating current to be considered as 40 uA or 20 uA?

The absolute maximum current on ICC is mentioned to be 100 mA in the datasheet.

Kindly suggest as it will help us decide minimum pcb trace width for VCC supply on TCA9548A in our design. Many thanks!

  • 0
    TI__Guru 53028 points

    Hi Trushal,

    The ICC spec is based upon the current consumption through the device while there is no load on the outputs. Note that all output currents "Io" are equal to 0 A. 

    The delta ICC (supply-current change) is defined as the increase in supply current for each input that is at one of the TTL voltage levels rather than 0V or VCC. This is specific to SDA and SCL pins.

    The current through ICC will change based upon the load that is present. This changes with respect to the load that is connected to a specific output pin. For example, a resistive load of 1kohm when the output pin is high at 5V will draw more current than a resistive load of 10kohm. This calculation has to be done in the designing of the system application. 

    The absolute maximum current that this device can handle before potentially causing permanent damage to the device is listed in the absolute maximum conditions in the datasheet. This value is +/-100mA ICC. I would be more cautious of the input/output current specs since they are much lower. The maximum current that can pass through one channel of this device is -25mA. Anything more, and the device is subject to permanent damage since the device was operated outside absolute maximum conditions. 

    Regards,

    Tyler

  • 0 in reply to Tyler Townsend
    Prodigy 140 points

    Hi Tyler,

    Thanks for the comment. So with delta ICC of 20 uA, if we use all 8 channels, overall ICC will come out to be 20 uA  + 8 * 20UA = 180 uA for 2.7V VCC?

    I assume -25mA you mentioned is the sink current(Logic 0) and will be passed on from high voltage side to low voltage side or through ground pin of TCA9548A. So return path on PCB for ground pin should be strong enough to support around -200 mA (8 channels). We have thick connection to GND pin in our pcb . Our concern is more about minimum trace width on VCC pin. We have a long trace with small width from a voltage source to VCC pin.  Hence the current source current estimation is important. 

    Regards,

    Trushal

  • 0 in reply to Trushal Alshi
    TI__Guru 53028 points

    Trushal,

    Trushal Alshi said:
    Thanks for the comment. So with delta ICC of 20 uA, if we use all 8 channels, overall ICC will come out to be 20 uA  + 8 * 20UA = 180 uA for 2.7V VCC?

    The delta ICC supply current change spec is defined as the additional current flowing into the VCC terminal when a voltage that is not 0V is applied to the SDA/SCL pins. IN this case, the test spec is 0.6V at the input. So, this voltage input causes more current to flow into the VCC pin. This is not a spec that concerns all 8-channels. The calculation you provided would not apply to this spec. 

    Trushal Alshi said:
    I assume -25mA you mentioned is the sink current(Logic 0) and will be passed on from high voltage side to low voltage side or through ground pin of TCA9548A. So return path on PCB for ground pin should be strong enough to support around -200 mA (8 channels). We have thick connection to GND pin in our pcb . Our concern is more about minimum trace width on VCC pin. We have a long trace with small width from a voltage source to VCC pin.  Hence the current source current estimation is important. 

    Theoretically yes, the PCB return path for the ground pin should be strong enough to withstand -200mA if all 8 channels were active. The problem is I don't think you will be able to source -200mA without causing ICC to sink <100 mA. I would think the drive capability on the gate of the passFETs internal to the device, and the power dissipation from a large current passing through the RDS_ON of many active FETs would cause the ICC to increase before you could pass total 200mA through the device. 

    I recommend to customers to make the GND and VCC pins as wide as possible without being cumbersome when designing the PCB.

    Regards,

    Tyler

  • 0 in reply to Tyler Townsend
    Prodigy 140 points

    Tyler,

    Thanks. Assuming that we have pulled up all outputs to a higher voltage level 3.3V through 4.7 kohm, I_ol=  (V_dpux - V_ol_max)/R_p = 0.64mA (assuming V_ol_max = 0.3V), for 8 channels, overall I_ol = 0.64 * 16 = 10 mA. So for -10 mA, can I_CC be assumed to be < 5 mA? There is a graph of V_ol against I_ol on page 9 of the datasheet. Not sure if corresponds to a particular value of R_p. Not sure if I am following you. 

    Regards,

    Trushal

  • +1 in reply to Trushal Alshi
    TI__Guru 53028 points

    Hi Trushal,

    I see the calculation of 3.3V through 4.7k pullup resistor yields a 0.64mA current draw assuming VOL = 0.3V. For 8 active channels, this result shows to be 16 x this current which is 10.24mA. This is the current through the passFETs internal to the device, but this does not necessarily effect the current consumption through ICC. I would think that passing 10.24mA of current through the IO's of the device would not have much effect on ICC (maybe only uA of change).

    I would suspect that most of the current draw through device VCC would be when SDA/SCL signals are oscillating during I2C communication. This is a result of CMOS circuity producing the most power dissipation during the midpoint of the Vgs threshold voltage. As you may know, an increase in Vgs for an NFET produces an increase in drain current ID. For a pFET, an increase in Vgs reduces the amount of drain current. Combining these two types into a CMOS input, causes current dissipation to become highest when crossing that threshold. When an I2C datastream that oscillates, it crosses this boundary rapidly, causing more current consumption through ICC. 

    Regards,

    Tyler

  • 0 in reply to Tyler Townsend
    Prodigy 140 points

    Hi Tyler,

    Thanks. It indicates that the switching logic is consuming much of the ICC. I was expecting the current to be used to charge the gates of pass transistors which should run in few uA. As there is no such  parameter or value mentioned for particular R_p, V_dupx and I2C frequency in the datasheet, we have to go with 100 mA . 

    Regards,

    Trushal 

  • 0 in reply to Trushal Alshi
    TI__Guru 53028 points

    Hi Trushal,

    I wish I could give a more clear cut answer on the amount of current used at each gate of the internal passFETs but this is something we do not necessarily spec. 

    Regards,

    Tyler

  • 0 in reply to Tyler Townsend
    Prodigy 140 points

    Hi Tyler,

    Thanks for the prompt support.

    Regards,

    Trushal