Other Parts Discussed in Thread: DP83869, AM6442
I am seeing high (>10%) packet loss using DP83869 in RGMII to Copper mode at 1Gbps. I originally saw this issue using a custom board, but have also been able to duplicate this problem on TI's AM64EVM board. I've narrowed down the problem to what appears to be some kind of FIFO overflow in the PHY when operating at 1Gbps.
With TI's AM64GPEVM board I can duplicate the problem by transmitting a 1516 byte packet repetitively (using PRU core to achieve low latency transmit). I have the IPG configured for 192ns, which is double 96ns to ensure no IPG issues. I've also verified the IPG by looking at time between packets on the wire. I am currently only transmitting packets (no RX) to simplify debugging. Packets are captured on the wire using a ProfiShark 1G+.
The problem occurs after transmitting 73 packets (1516 bytes each) successfully back to back with 192ns IPG between each packet. After this, packets 74 and 75 are always dropped (not seen via Profishark tap). I do see packets 74-75 between MAC and PHY via oscilloscope on the RGMII TXC/TXD lines. After dropping packets 74-75, packet 76 is successfully seen on the wire. Thereafter roughly 7-8 packets are dropped for every 30 packets sent. Since I've seen this problem on multiple boards and even different PHYs on the same board, this appears to be some kind of FIFO overflow issue in the PHY.
If I reduce the transmit speed (one 1516 byte packet every 20us, every 50us, every 100us...) the packet loss improves. If I send fewer than one 1516 byte packet every 200 microseconds, the problem goes away entirely. Here are other ideas I've tried:
1. Verified the PHY is configured per the datasheet section 9.4.8.1 for RGMII to Copper (BCMR=0x1140, PHY_CONTROL=0x5048, GEN_CFG1=0x300)
2. Verified I'm using TI's provided value for TX clock shift on the ICSSG ports of the AM64EVM board (750ps)
3. Tried varying the TX CLK shift. It does not seem to have an impact until it is >1500ps, at which point I read garbage data on the wire (as expected).
4. Tried 0x1, 0x2, and 0x3 values in TX_FIFO_DEPTH for PHY_CONTROL register 0x10. Although the datasheet comment seems to indicate TX_FIFO_DEPTH doesn't apply for RGMII.
5. Checked INTERRUPT_STATUS register 0x13. I'm seeing the XGMII_ERR_STATUS, ADC_FIFO_OVF_UNF, and FALSE_CARRIER bits set.
What else can I do to troubleshoot this problem?
