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SN65LV1023A: Question about sn65lv1023a and 1224b chip use

Part Number: SN65LV1023A

Hi Ti engineer,

I have some problems in the process of using, please help me to see where I made mistakes.

The usage scenario is as follows:
The timing diagram of the 1023a chip is shown in Figure 1

The configuration clock and pin level of the 1224b chip are shown in Figure 2:

 1023a  and 1224b Schematic diagram:

The questions are as follows:
1. Chip initialization operations mentioned in the manual Do the pwrdn pins of both chips need to be pulled down for a period of time and then pulled up to complete the initialization?
2. Answer question 1, how long will it take to pull down?
3. Connect to question 1. Do you need to perform initialization only once after power-on? Or every 1206 output data needs to perform an initialization operation.
4. My 1224b no clock and data output is missing which step?
5. Please help to see if there is any problem with the chip circuit.

  • Hello,

    1 and 2) There isn't a specific period of time the pwrdn pins need to be pulled down. Just note pwrdn needs to be high to start initialization. 

    3) Yes that's correct. Please see image above. You can't perform initialization when pwrdn is low since Lock, Rout and RCLK will be in a high-impedance state.

    5) Please see EVM User's Guide for schematic reference.

    One note: Please make sure REFCLK and TCLK clock tolerance is at or below ± 100 ppm. Having a higher tolerance will cause Lock issues.

    Regards,

    Josh