DS90UB949A-Q1: DS90UH949A datasheet question

thanks Cameron

question2, I want to know 0.1uF, if RC need long time, example R3 =118K, R4 = 30.9K, so RC = 118*0.1，it need time for charge the 0.1uF, i want to know the time for IC internal sampling these, it must bigger than RC charge time.

Hi Songlin,

I am going to consult with my team about this and get back to you after July 4th.

Best,

Cameron Carlson

Hi Songlin,

So long as you are following the recommended power-up sequence, it will already cover the sample time for these pins.

One way to double check is to read registers 0x00 and 0x5B. Register 0x00 will give the device ID, which will show whether or not your IDX pin is strapped correctly. Bit 7 of register 0x5B will give the FPD3 Coax Mode, if this is read correctly, then it will verify that your mode_straps are set correctly. As mentioned before, this is only to double check as the device will already cover the sampling time for these pins if the recommended power-up sequence is followed.

Please let me know if you have any other questions.

Best,

Cameron Carlson

Cameron Hoholik-Carlson said:

it will already cover the sample time for these pins.

when power up, it will need time to sampling

Cameron Hoholik-Carlson said:

After a PDB reset, there is no additional wait time needed.

after PDB, it's sampling ok? so time between power up VDDIO and PDB the sampling down ? but t2 minimal 0ms.

Hi Songlin,

Per the datasheet sampling, the PDB signal must go high after the power rails are stable and high. After this point, yes, sampling is okay.

Best,

Cameron Carlson

but still not explain when the sampling time？

Hi Songlin,

There is no sampling time for powering on the device, as there isn't a set polling/sampling rate that the device checks PDB at.

Please refer to the power sequencing for proper operation of the device. PDB must be high after power supplies are fully high and stable (>0ms), but outside of this there is no sampling time requirements from VDD to PDB high.

songlin he said:

so time between power up VDDIO and PDB the sampling down ? but t2 minimal 0ms.

T2 indicates PDB needing to go high after VDD rise.

Best,

Cameron Carlson

Still don't understand this, when power up, it will need maybe 1ms for sampling IDX or MODE_SEL pin value? 

So 0.1uF is fine, for all IDX/MODE_SEL choose? even pullup resistor over 100K.