• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 34 subscribers
  • Views 157 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90UB928Q-Q1: DS90UB928Q-Q1

yali.2.zhou
Prodigy 10 points
Part Number: DS90UB928Q-Q1

hello，

May I ask you some questions for below picture.

1. Channel4 is CLK (17 pin), I want to know why the CLK signal have three steps. why the DESERIALIZER enable has not be up high, the clock signal has be up high.

how can we disable the data.

2. When 3V3G is low, the CLK signal is already present, will it affect DESERIALIZER to enter self protection black screen?

3. I want to confirm if PDB pin is up high, the clock start to output. the step rise stage DESERIALIZER is not working properly.

  • 0
    TI__Guru** 107610 points

    Hello Yali,
    Because of the Fourth of July holiday, TI E2E design support forum responses may be delayed from July 3 through July 4. Thank you for your patience.

  • 0
    TI__Intellectual 2535 points

    Hi Yali,

    I have a couple of questions about your configuration. Firstly, what serializer are you connecting the 928 to? In addition to this, was the deserializer connected to a display when this capture was taken?

    Secondly, can you tell me what channel 1 and 2 represent and are connected to? This can help me confirm what the correct sequencing is after enabling PDB. In addition to this, could you please include the OEN signal in your next capture? I would like to see how that signal is behaving during this sequence.

    Best,

    Cameron Carlson