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TCAN4551-Q1: Application issues of chips

Tonyx.wu
Genius 3915 points
Part Number: TCAN4551-Q1
Other Parts Discussed in Thread: TCAN4550-Q1

I have a question to ask. The meaning of this sentence is: If we use an IO voltage of 1.8V, we cannot use crystals, right?

Why should an external clock be used instead of a crystal when VIO=1.8V?

If I don't have an external clock and want to use a 1.8V VIO, can I hang a 1.8V powered TCXO? If not, are there any other methods that can meet my application needs?

  • Genius 3915 points

    Do these questions have any results?

  • in reply to Tonyx.wu
    TI__Mastermind 33030 points

    The TCAN4551-Q1's clock circuitry is powered from the VIO supply pin that also provides the voltage reference for the digital IO levels on the SPI and other digital IO pins.  The TCAN4551-Q1 is based on the TCAN4550-Q1 device that only supports a VIO = 3.3V, or 5V and has a UVIO specification and a UVLO feature with 2.1V to 2.6V window. This is needed to ensure the transistors in the crystal oscillator amplifier have enough overhead voltage to avoid saturation and to work properly.  However, this prevents the TCAN4550-Q1 from working with a 1.8V digital IO voltage level.

    This UVIO and UVLO feature has been removed from the TCAN4551-Q1 that allows it to support 1.8V, but this also means that the clock circuitry may not work properly with a crystal and therefore a single-ended clock should be used when VIO = 1.8V.

    Any single-ended clock at the correct frequency (typically either 20MHz or 40MHz) that swings between 0V and VIO would work.  The min/max spec's are a percentage of VIO, so they change with the VIO voltage.  For 1.8V, the low voltage should be lower than 0.54V, and the high voltage level should be greater than 1.53V.

    A TCXO that provides a signal that meets these voltage requirements would certainly work.

    Regards,

    Jonathan

  • in reply to Jonathan Nerger
    Genius 3915 points

    Please help me check if this schematic diagram is correct. Thank you!

  • in reply to Tonyx.wu
    TI__Mastermind 33030 points

    I've reviewed the schematic and have the following comments:

    • Note that RST is an active high signal that should be held low during normal operation.  Pulsing it high will cause the device to have a POR.  It is normal to have a pull down resistor instead of a pull up resistor on this pin.  As configured, your "4G_CAN_RST" net will have to continuously sink current to hold the CAN_RST pin low to prevent the R451 pullup resistor from resetting the TCAN4551.  I don't know if this was your intent.
    • We recommend adding a series resistor between the OSC1 pin and the crystal to help optimize the clock circuit.  Please see the TCAN455x Clock Optimization and Design Guidelines application note for more information. 
    • I'm not sure if the SPI SDO and SDI data pins are in the correct configuration because TXD and RXD are not common SPI net names.  If TXD is the the data transmitted from the MCU to the TCAN4551, and the RXD is the data to be transmitted from the TCAN4551 to the MCU, then the configuration would be correct.  You may want to double check this is correct.
    • It is common to have a weak pull up resistor on the nCS pin to make sure that the SPI chip select signal remains high when idle.  This is optional.

    Regards,

    Jonathan