DS90UB948-Q1: TFT power-on sequence issue

Hale Tan

Part Number: DS90UB948-Q1

Hi team,

The customer have a display screen project with 948. When doing the TFT power-on sequence, they found that: LVDS will output a high level to the screen as soon as the 948 is powered on (green in the figure below), which leads to backflow of STB RST and other signals of the screen. What is the reason for this LVDS pull-up, and is there a way to turn it off?

over 2 years ago

0 Ben Dattilo over 2 years ago

TI__Mastermind 25765 points

Hi Hale,

Which pin is this happening on?

Do you have the 100Ohm termination as listed in the datasheet?

Regards,

Ben Dattilo

0 Hale Tan over 2 years ago in reply to Ben Dattilo

TI__Expert 3770 points

As the picture showing, the LVDS clk pin and D0-D7 all has high level voltage when the display is power-on. We want to make sure why there is high level voltage. And STB, RST and other signals of the screen are not 948 signal. Do you have any clues and do we have anything else need to check?

0 Hale Tan over 2 years ago in reply to Ben Dattilo

TI__Expert 3770 points

Hi Ben,

The customer replied that when they power on the 948, the LVDS will output high level voltage even if they don't configure the 948. And I will send the schematic to you via email. Do you have any suggestion?

0 Ben Dattilo over 2 years ago in reply to Hale Tan

TI__Mastermind 25765 points

Hi Hale,

The high level LVDS on startup is normal and expected. I will reach out over email for a potential work-around.

Regards,

Ben

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DS90UB948-Q1: TFT power-on sequence issue