Hi team,
my customer use this mode, CLK_IN configured as 32MHz input,
use below marked GREEN to create CLK_OUT=24MHZ
then they test 32MHz active crystal : AVG: 31.997MHz, MAX: 32.051MHz, MIN: 31.948MHz.
The test CLK_OUT is 23.75MHZ~24.25MHZ.Is this error within reasonable limits？ If not, please help to analyze the cause of this large error
thanks
Hello Hazel,
In section 7.4.1.5 Configuring CLK_OUT in the DS90UB935-Q1 datasheet, it states that there will be very low jitter if the ratio N/M is an integer.
In this case, you are using N=80 and M=3, which results in (N/M) not being an integer. If you adjust the (N/M) values to be an integer, then there should be less variation.
Best,
Justin Phan
