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DS90UB935-Q1: CLK_OUT error

Hazel Sun
Expert 6535 points
Part Number: DS90UB935-Q1

Hi  team,

my customer use this mode, CLK_IN configured as 32MHz input, 

use below marked GREEN to create CLK_OUT=24MHZ

then they test 32MHz active crystal : AVG: 31.997MHz, MAX: 32.051MHz, MIN: 31.948MHz. 

The test CLK_OUT is 23.75MHZ~24.25MHZ.Is this error within reasonable limits？ If not, please help to analyze the cause of this large error 

thanks

  • 0
    TI__Mastermind 28100 points

    Hello Hazel,

    In section 7.4.1.5 Configuring CLK_OUT in the DS90UB935-Q1 datasheet, it states that there will be very low jitter if the ratio N/M is an integer.

    In this case, you are using N=80 and M=3, which results in (N/M) not being an integer. If you adjust the (N/M) values to be an integer, then there should be less variation.

    Best,

    Justin Phan

  • 0 in reply to user6283026
    Prodigy 50 points

    Hi  Justin 

    Thanks for replying! 

    When CLKIN was proposed before the selection of 48MHz/36MHz/32MHz, the impact error on the output CLKOUT. You can only reply as follows. I think that 36MHz is similar to 36MHz, so I chose 32MHz. Why did not explain this point at that time? Now that this problem is too late, the product can't be changed. If the hardware does not change 32MHz now, is there any software method to reduce the CLKOUT frequency error?

    CLK_IN = 48 MHz, Expected Jitter = 1.041666667 ns

    CLK_IN = 36 MHz, Expected Jitter = 1.388888889 ns

    CLK_IN = 32 MHz, Expected Jitter = 1.5625 ns

    thanks!

    qingzhi.li

  • 0 in reply to user6283026
    TI__Mastermind 28100 points

    Hello,

    I believe you are referring to the response from this post:

    https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1200483/ds90ub935-q1-if-there-is-any-difference-when-clk_out-is-the-same-frequency-error-is-0/4526710?tisearch=e2e-sitesearch&keymatch=CLK_IN%2520%253D%252032%2520MHz%252C%2520Expected%2520Jitter%2520%253D%25201.5625%2520ns#4526710

    The math for CLK_OUT is defined in the datasheet, where if the (N/M) values are an integer, then the jitter is expected to be very low. If (N/M) are not an integer, then the jitter on the CLK_OUT signal is expected to be approximately equal to  HS_CLK_DIV/FC.

    Assuming you are using a 32MHz REFCLK (CLK_IN = 32MHz) and you are operating in Non Synchronous External Clock Mode, the FC rate will be (CLK_IN x 80) = 2.56Gbps (See Table 7-7. Clocking Modes in the 935 datasheet).  Since HS_CLK_DIV is set to the default value of 4, then the expected jitter in your application is (4 / 2.56Gbps) = 1.56ns.

    The desired CLK_OUT frequency is 24MHz.

    There are 2 ways to approach this.

    1. Check with the imager datasheet and see if the imager can tolerate a 24MHz signal with approximately 1.56ns of jitter. If you need less jitter, you can set the HS_CLK_DIV value to be lower and increase the N value in registers 0x06-0x07, to get the same CLK_OUT frequency but less jitter. And then measure the jitter in your system, to see if the imager accepts that level of jitter.
      2. EDIT: I meant decrease HS_CLK_DIV, but increase the N value, to get the same CLK_OUT frequency and a lower HS_CLK_DIV value.
    2. You can change the M and N values to make sure (N/M) is an integer. However, this may mean that the CLK_OUT frequency will not exactly be 24MHz. Check to see what range of frequencies the imager can accept as its reference clock.

    Best,

    Justin Phan