In our project, we plan to use the TI DP83869HM 10/100/1000 Ethernet Physical Layer Transceiver in SGMII functional mode, which offers tri-speed functionality, by connecting it to an FPGA device.
According to the datasheet, the DP83869HM PHY employs a frame elongation technique, where each frame byte is replicated 10 times for 100-Mbps and 100 times for 10-Mbps.
Interestingly, the start of frame delimiter appears only once per frame.
In our analysis of other vendors' PHY datasheets, we noticed that they did not mention a similar implementation of the start of frame delimiter appearing once per frame.
Instead, their datasheets generally indicated the repetition of each byte in the frame 10/100 times.
we are interested to know if this chip is compatible with standard FPGA PCS/PMA & MAC IP Cores, particularly regarding the Start of Frame Delimiter (SFD) aspect in tri-speed operation.
Additionally, we are curious to know if this frame elongation process adheres to a specific industry standard or if it is a unique implementation by Texas Instruments (TI).
Your clarification on these matters would be highly appreciated. Thank you.
