• State Answer Suggested
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 33 subscribers
  • Views 207 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

XIO1100: Suggest clock level translator

Nandhini Anandan
Prodigy 120 points
Part Number: XIO1100

Hi,

We have selected the mentioned PCIE PHY (XIO1100ZWSR) for our design, and for REFCLK+ and REFCLK- we are planning to provide 100MHz differential clock for both PCIE PHY and PCIE Finger edge (End Point) separately.

So, the clock generator which we have chosen (MPN: DSC557-0344FL1) is 3.3 IO Voltage level, so we need a suitable clock level translator for the PCIE PHY (1.8V).

PCIE Finger edge IO level is 3.3V so no need of level translator.

Kindly suggest the PCIE DIFFERENTIAL CLOCK LEVEL TRANSLATOR.

Regards,

Nandhini A.

  • 0
    Guru 317370 points

    Even when the DSC557-0344FL1 uses a 3.3 V supply, its outputs are HSCL and use lower voltage levels (see its VOL/VOH specifications).

    As far as I can see, you can connect the clock generator directly to the REFCLK inputs. (See the DSC557 datasheet for correct termination. And the traces should be impedance controlled.)