SN65DP159: OUT_CLK duty cycle

Ruixin Feng

Part Number: SN65DP159

Hi team,

In datasheet spec, when SN65DP159 in retimer mode, duty cycle of out_clk is 40%-60%, but we test on EVM and the result is 37.5%. May I know the reason? Could you pls help to check it on EVM?

Thanks!

Rayna

over 2 years ago

0 Zach Dryer over 2 years ago

TI__Genius 13310 points

Hello,

Please see this app note, https://www.ti.com/lit/an/slla358/slla358.pdf. You can tune other characteristics of OUT_CLK such as the output VOD using the VSADJ resistor, but can't change the clock duty cycle.

Thanks,

Zach

0 Ruixin Feng over 2 years ago in reply to Zach Dryer

TI__Intellectual 2395 points

Hi Zach,

Yes, that's what customer has followed. But the test result is not what datasheet shows. You may refer to the test results in attached file. Thanks!

DP159时钟FPGA接收端刮孔测试结果.docx

Thanks!

Rayna

0 Zach Dryer over 2 years ago in reply to Ruixin Feng

TI__Genius 13310 points

Rayna,

Can you share their schematic?

Thanks,

Zach

0 Ruixin Feng over 2 years ago in reply to Zach Dryer

TI__Intellectual 2395 points

Hi Zach,

Customer used our EVM board for test .

Rayna

0 Zach Dryer over 2 years ago in reply to Ruixin Feng

TI__Genius 13310 points

Rayna,

There is no way to change the clock duty cycle. I can check internally and get back to you.

Thanks,

Zach

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SN65DP159: OUT_CLK duty cycle