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DS90UB948-Q1EVM: Artifacts on LVDS output

Alex Jones
Prodigy 10 points
Part Number: DS90UB948-Q1EVM
Other Parts Discussed in Thread: ALP, USB2ANY

To whom this may concern, 

I am trying to use the DS90UB948-Q1EVM eval board with a 1080p 60Hz display. I was able to get the pattern generator to display images on the screen, but a few artifacts are present. Notably, there are two columns of horizontal pars that run down the middle of the screen. It also appears that the picture on one side of the screen is inverted (this can be seen when generating the VCOM pattern).

I've connected the eval board to the screen with the following LVDS configuration:


I'm using the AUO G173HW01 V0 display, with 2-port LVDS interface. Here's the pinout of the display connector:

These are the ALP parameters I'm using:

 

I'm currently operating with switch S1 (MODE_SEL0) setting as S1.7 on, all others off. I've attached an image of the evaluation board:

Do you have any idea as to what could be causing the artifacts? 

Regards,

Alex

  • 0
    TI__Mastermind 34085 points

    Hi Alex,

    From the image of the EVM, I can see you are operating in Dual OLDI model with MAPSEL = H. Does this artefact appear for every pattern generated by the PATGEN?

    I looked over the display datasheet and saw that it is intended to support Hi-FRC. There is an option in the UB948 to support Hi-FRC in register 0x29. Could you try enabling Hi-FRC1 in that register?

    Best,

    Jack

  • 0 in reply to Jack Scherlag
    Prodigy 10 points

    Hi Jack,

    Thanks for your response. The artifact appears in all patterns generated by PATGEN. Both Hi-FRC1 and Hi-FRC2 were already enabled as shown below: 

    I tried all combinations of registers 3 - 0, with each of them yielding these artifacts.


    I've attached a register dump for your reference

    DS90UB948_Register_dump_072623.zip

    Regards,

    Alex

  • 0 in reply to Alex Jones
    TI__Mastermind 34085 points

    Hi Alex,

    The image you attached doesn't show Hi-FRC1 or Hi-FRC2 enabled. The boxes will need to be checked.

    Also, the register dump you sent says you are connected to ALP Nano 1, which indicates you are in demo mode. When you are connected to a device via the on board USB connector it should show a USB2ANY device.

    Do you see this when you are connected?

    Best,

    Jack

  • 0 in reply to Jack Scherlag
    Prodigy 10 points

    Hi Jack, 

    Both the datasheet and the description of the registers mention that setting bits 1 or 0 of register 0x29 low will enable Hi-FRC2 or Hi-FRC1, and setting them hi will disable Hi-FRC2 or Hi-FRC1. Regardless, I have gone through the 16 combinations of bits 3, 2, 1 and 0 or register 0x29 and all still show the artifact on the screen. 

    As for operating in Demo mode, It appears to be unchecked. I'll attach a screenshot of my ALP software:

    I hope this helps,

    Alex

  • 0 in reply to Alex Jones
    TI__Mastermind 34085 points

    Hi Alex,

    We can ignore the FRC controls for now. What is likely causing the artefacts is a timing mismatch between the PATGEN output and the display.

    The display you are using has the following typical timing characteristics

    • Htotal = 2100
    • HActive = 1920
    • Hblank = 180
    • Vtotal = 1130
    • VActive = 1080
    • Vblank = 50
    • Frame Rate = 60

    Are these programmed in the UB948 PATGEN?

    It is also important to note that there is a minimum refresh rate of 50 Hz for this display. The internal timing source in the UB948 is nominally 140 MHz, which limits the refresh rate of the PATGEN. In the app note SNLA132G, it lists the refresh rate of 1920x1080 timing of 30.4 Hz with an internal oscillator of 140 MHz. This is under the 50 Hz minimum for the display.

    My recommendation is to use a serializer connected to the deserializer to generate the PATGEN or use an external timing source. The FPD-Link III serializer PATGENs contain faster internal oscillators.

    Best,

    Jack