Hi
Actually, The LIN INTERFACE (TJA1020T/CM,118) we are using has TXD, RXD lines as Open-Drain which can support up to 3.3to 5V.
but FPGA interface has Pseudo-Open drain path i.e.,1.2V, we need this LIN interface to be compatible with the FPGA interface.
Could you please suggest us some level translator which can support the above query.
and please let me know it is possible to connect the SCL lines to receiver line.
