In my current project I have a signle board which shows a strange behavior on the MDI side of the ethernet PHY. Other boards doesn't have this issue and are running with 100Base-T Full Duplex with close to 100MBit/s throughput.So this is no design / layout issue in general.
The waveform on the picture I measeured at RD_P (yellow) and RD_M (turqouise). There was nothing plugged into the RJ45 connector, so this is an open measurement. This should be one FLP.
There is no swing in positive direction and the signal level goes much closer to 0V as on the other boards.
Do you maybe can help me to track down the root cause? The PHY IC itself seems to have everything he needs at his pins (voltages, clocks, etc).
AVD voltage is 3.3V, IO voltage is 1.8V.
If you need additional information please let me know.
Best Regards
Tim
