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Maximum trace lenght for 50MHz SPI communication

Other Parts Discussed in Thread: AM2434, LP-AM263

Hi team, 

My customer wants to know how long can TI's MCU can handle 50MHz SPI over PCB trace without using line drivers. Is there any app note that discuss about this topic?

Regards,

Ohashi

  • Ohashi-san, 

    What MCU are you asking about?  Since they are not using a buffer IC, we need to know the specific MCU being used.

    Arigato,

    ~Leonard  

  • Hi Leonard,

    Thanks for your comment. Pls assume that the customer is using AM24xx series. (maybe AM2434) 

    Regards,

    Ohashi

  • Hi Ohashi-san, 

    This sounds like a general transmission-line problem to me. We need some specifics from the AM2x MCU in question. My answer would be: 

    1. Find out what the 50 MHz SPI clock and data bandwidth requirements are and calculate the losses on a PCB transmission line at this loss (db/inch). Bandwidth of these digital signals is mostly a function of the edge-rate on our AM2x 3.3V I/O, this can be from 350-500pS if it is lightly loaded. You can get these edge-rates from our IBIS models [1].

    • Assuming a worse-case 350ps edge rate, this translates to about 1.4 GHz bandwidth for any of the digital signals on our devices [2]. 
    • You can change this by adding, overdamped, series termination or additional capacitance that will slow down the edge-rates even more [3]. This has the added benefit of also decreasing EMI radiation/susceptibility. 
    • Since transmission lines on PCB are lossy and loss is proportional to frequency, the higher the bandwidth of the signal, the more loss/inch it will see
    • So decreasing bandwidth with termination resistors is a good idea if you have longer runs

    2. Next, you can calculate the transmission line losses at the bandwidth of the signal and pick a loss threshold (attenuation) margin you are comfortable with.

    • The AM2x 3.3V LVCMOS I/O are all +/-5% tolerant, so assuming a nominal, well de-coupled power supply (negligible ripple) using maybe +/-2.5% is a reasonable margin.
    • So we can plan on 82.5mV drop or 20 * log ((3.3-0.0825)/3.3) = -0.219 dB losses. If you use the full -5% spec, then -0.445 dB.

    3. Then, using either a closed form equation estimate/tool like [4], or a 3D EM simulation, you can calculate the losses/inch of the transmission line in question.

    • If you use the LP-AM263 top layer 5.3 mil wide traces, on 3.5 mil Iteq IT 180A pre-preg, you get about 0.137dB/inch loss @ 1.4GHz, or 7.299 inches/dB
    • 7.299 inches/dB x 0.219 dB  = 1.6 inches
    • If you decrease the edge-rate to 500pS, or 1GHz bandwidth, this increases the length to 8.673 inches/dB x 0.219 dB = 1.9 inches

    Further increases in transmission line length are possible by using series termination to slow down the edge-rate further, decrease the max operating bandwidth, and therefore operating in a lower frequency, less lossy region of the transmission-line. Also, higher speed substrates with better dielectric constants and loss tangents will decrease the losses across frequency as well. 

    [1] AM263x Sitara IBIS Model https://www.ti.com/lit/zip/sprm771 

    [2] Johnson, Howard and Martin Graham, High-Speed Digital Design: A Handbook of Black Magic, Prentice Hall, 1993. Summarized here: https://eepower.com/technical-articles/understanding-bandwidth-requirements-when-measuring-switching-characteristics-in-power-electronic-applications/# 

    [3] TI Precision Labs "PCB trace impedance matching" https://www.youtube.com/watch?v=DKxDCO1kLEs 

    [4] Wcalc: a tool for the analysis and synthesis of transmission line structures and related components https://wcalc.sourceforge.net/