DP83869HM: Clock Jitter Specification for DP83869

Hi Brendan,

Your interpretation of the table is correct and the statement made in the datasheet remains true. You can use the Output Clock from one 869 as the Input Clock for another 869.

Regards,

Alvaro

Hi Brendan,

The Input Jitter Tolerance (100k Cycles) is relatively short term, the long term Jitter specced in Output Clock Timing is from a much longer period. 

I understand the confusion. Again, it is okay to use the Output CLKOUT Signal from one 869 as the Input Clock for another 869.

Regards,

Alvaro

Hi Brendan,

We admit that jitter specs of input and output clocks are not clear enough for apple to apple comparison when using one PHY’s clock output for another’s clock input. We checked with the team and hopefully following notes will help you move forward with clock daisy chain evaluation :

1. 25MHz output phase noise/jitter looks like this:

This indicates ~5ps Rms jitter and ~70ps pk-pk jitter.

 2. 25MHz input clock requirement is as follows:

With 11ps of  RMS  jitter tolerance (bw : 12KHz to 5MHz)

Above two data points indicates that output of 869 can be the valid input for other 869.

Regards,

Alvaro

Hi Brendan,

You're welcome, it was a helpful learning for me too.

Yes, the PLL will clean up the clock.

Regards,

Alvaro